RT1024 Double bank with memory offset

[Gaetan]

In our system, we have RT1024 and RT1064 processors.
For each microprocessor, we implemented a dual-bank bootloader mechanism to handle updates.
Since our code is quite large, we cannot execute it from RAM and instead execute it from flash.
Our images are compiled with static addresses corresponding to bank one.
When image two boots, we want to perform an address translation.
There is a simple solution for the RT1064 that involves using the IOMUXC_GPR_GPR30, 31, and 32 registers.
The operating principle is explained in the following documentation:
https://www.nxp.com/docs/en/application-note/AN12240.pdf
However, we haven't found an equivalent mechanism for the RT1024.

Does one exist?

If not, do you have a solution to suggest?

[Gaetan]

I found a post similar to my needs:

https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/imx-rt-1024-position-independent-code/m-p/144824...

However, I can't get it to work. Here are the steps I took:

I started a project from scratch with only a flashing debug LED. Modified the linker:

Setting the compilation options:

Adding the correct reference in the r9 register:

I load the .bin file at address 0x60080000 I created a bootloader project with only a jump to address 0x6008238D, which is the address of the reset handler 0x6000238D + the offset.

During the jump, the code fails.

I must be missing an operation, can you help me?

[Gaetan]

One thing that seems strange to me is the contents of the .map in the .got section.
I don't know if it's normal for there to be so little.

[Gaetan]

I think I'm close to the goal.
I've hard-coded all the values into the startup file.
When I disassemble the code, something seems strange: the function addresses are static despite the -pFIC option.