RT1020 flash operation SDK example Question

[Seongyon_Jeong]

Hi

from flash SDK example, 

My question is About flexspi_clock_init.  

static inline void flexspi_clock_init()
{
#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
    /* Switch to PLL2 for XIP to avoid hardfault during re-initialize clock. */
    CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); /* Set PLL2 PFD2 clock 396MHZ. */
    CLOCK_SetMux(kCLOCK_FlexspiMux, 0x2); /* Choose PLL2 PFD2 clock as flexspi source clock. */
    CLOCK_SetDiv(kCLOCK_FlexspiDiv, 2); /* flexspi clock 133M. */
#else
   ~~~~
#endif
}

In this function  ,   flexspi clock is 132Mz , isn`t it ?   why  133,000,000 ?,   

Does not it make wrong action ?

/*******************************************************************************
* Code
******************************************************************************/
flexspi_device_config_t deviceconfig = {
.flexspiRootClk = 133000000,
.flashSize = FLASH_SIZE,
.CSIntervalUnit = kFLEXSPI_CsIntervalUnit1SckCycle,
.CSInterval = 2,

[EdwinHz]

Hi @Seongyon_Jeong,

The output from the flexspi_clock_init() should be 133MHz. Are you seeing a 131MHz output from your board? Or how are you determining that your output is different from the intended frequency?

BR,
Edwin.

[Seongyon_Jeong]

I didn`t  check the frequency [directly - physically] using scope.  

Just only,  with Software description.,

CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); => PLL2 PFD2 clock 396 Mhz
CLOCK_SetMux(kCLOCK_FlexspiMux, 0x2); /* Choose PLL2 PFD2 clock as flexspi source clock. */
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 2);
=> Exactly [ PLL2 PFD2 clock 396 Mhz ] / 3 = 132Mhz , why Say 396 / 3 = 133Mhz ???

[EdwinHz · Accepted solution]

Hi @Seongyon_Jeong,

You are correct. From the software description it does seem to be 132MHz, but after replicating the setup on ConfigTools' Clocks tool, I also got the same 132MHz. I believe 133MHz is one of the standard values supported from flash devices. However, most likely for simplicity the flexspi_clock_init() routine initially sets it to a near acceptable value of 132MHz. That said, I will comment about this internally to chance the comment to the appropriate frequency.

Thanks for reporting this.

BR,
Edwin.

[Seongyon_Jeong]

thanks for your explanation.