RGMII power

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RGMII power

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vadimaleynikov
Contributor III

Hello.

If the NVCC_RGMII1 and/or NVCC_RGMII2 pins of iMX6SX can be not powered (some time or totally)?

Best regards,

Vadim Aleynikov

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igorpadykov
NXP Employee
NXP Employee

Hi Vadim

board design was done when not all documentation was ready,

also for i.MX6SX Table 2-17. Recommended connections for unused analog interfaces

there is no RGMII

http://www.nxp.com/files/32bit/doc/user_guide/IMX6SXHDG.pdf 

Best regards
igor

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3,043 次查看
igorpadykov
NXP Employee
NXP Employee

Hi Vadim

board design was done when not all documentation was ready,

also for i.MX6SX Table 2-17. Recommended connections for unused analog interfaces

there is no RGMII

http://www.nxp.com/files/32bit/doc/user_guide/IMX6SXHDG.pdf 

Best regards
igor

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vadimaleynikov
Contributor III

Thank you Igor very much.

Best regards,

Vadim

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igorpadykov
NXP Employee
NXP Employee

Hi Vadim

all power supplies should be provided to processor

with exceptions given in Table 2-21. Recommended connections

for unused analog interfaces i.MX6 System Development User’s Guide

http://cache.freescale.com/files/32bit/doc/user_guide/IMX6DQ6SDLHDG.pdf

Best regards
igor
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vadimaleynikov
Contributor III

Hi Igor.

Thank you for the reply. Table 2-21, which you referred to, contains RGMII. If my understanding is correct, then this means that the RGMII can be left unpowered when it isn't used. Please confirm or correct me.

Best regards,

Vadim

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igorpadykov
NXP Employee
NXP Employee

Hi Vadim

Table 2-21 does not show that RGMII can be left unpowered.

It should be powered even not used.

Best regards
igor

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vadimaleynikov
Contributor III

Hi Igor.

Unfortunately your answers are not quite clear to me. In the first reply you wrote:

"all power supplies should be provided to processor with exceptions given in Table 2-21"

Table 2-21 contains the RGMII module, but in the next reply you wrote: "Table 2-21 does not show that RGMII can be left unpowered." It seems to me that these statements are not quite consistent.

Does Table 2-21 presents exceptions of the power supplies which must be provided or not?

Then, in the NXP Reference Design schematics ( MCIMX6SX SDB: SPF-27962.pdf), the iMX6SX RGMII modules are supplied by  Ethernet PHY chips U18 and U19. And power supplies of U18 and U19 are under software control by signals PERI_PWR_EN and ENET_PWR_EN_B; both these signals are inactive on default. So, on the MCIMX6SX SDB the NVCC_RGMII1 and NVCC_RGMII2 may be not powered totally or at least, they will not be powered all the time depending  on the used software.

If this (SPF-27962.pdf) implementation of RGMII and PHY power is correct?

If the iMX6SX RGMII modules can be not powered at least a part of the system operation time?

Best regards,
Vadim

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