Hi Igor.
Unfortunately your answers are not quite clear to me. In the first reply you wrote:
"all power supplies should be provided to processor with exceptions given in Table 2-21"
Table 2-21 contains the RGMII module, but in the next reply you wrote: "Table 2-21 does not show that RGMII can be left unpowered." It seems to me that these statements are not quite consistent.
Does Table 2-21 presents exceptions of the power supplies which must be provided or not?
Then, in the NXP Reference Design schematics ( MCIMX6SX SDB: SPF-27962.pdf), the iMX6SX RGMII modules are supplied by Ethernet PHY chips U18 and U19. And power supplies of U18 and U19 are under software control by signals PERI_PWR_EN and ENET_PWR_EN_B; both these signals are inactive on default. So, on the MCIMX6SX SDB the NVCC_RGMII1 and NVCC_RGMII2 may be not powered totally or at least, they will not be powered all the time depending on the used software.
If this (SPF-27962.pdf) implementation of RGMII and PHY power is correct?
If the iMX6SX RGMII modules can be not powered at least a part of the system operation time?
Best regards,
Vadim