RAW10 (SBGGR10) support in imx8qxp

[wasim_nazir]

Hi,

I am facing problem in getting proper data from camera (RAW10bit, 2lanes) using MIPI-CSI-0. In each pixel(16bits), 4-MSB bits are getting discarded.

Input & output formats of ISI is set to RAW10

Anyone else is facing the same issue with RAW10 format in imx8qxp? Any lead is appreciated.

Thanks

[Bio_TICFSL]

Statement 1 is right.

-----

• If I receive a RAW10 stream, how data will be packed in memory after the ISI (shift + number of byte to be used to have the full data)?

     MIPI subsystem RAW10 output format is  {valid_data, 4’b0} . After right shift 4 bits, you will get the correct image.

-----

There is a mistake in the RM, I´ll ask to fixed. Thanks for the catch.

Regards

[pmliquify]

Hello, I have the same Problem with an imx8qxp on a ConnectCore8X Board from DIGI Embedded. I do use a Sony IMX327C with 2 lanes over the mipi_csi_0 channel.

In my case i have to set the CHNL_IMG_CTRL[0x04] Register to 0x0f000001 (RAW16 and CSC_BYP enabled) to obtain all bits of the image. When I set it to RAW10 I lose 4 MSBs and when I use RAW12 I lose 2 MSBs. As described above all bits are shiftet 4 bits left. I implemented the 4 bit right shift in software in my demo application. This is very slow but shows the correct image. 

For me it looks like the CSI-2 Data formats layer isn't working properly.

My quest now is, how to solve this problem.

1. Is there a posibility that the isi and/or csi delivers not shiftet images?
2. How can I debug the data_out register (local interface) of the MIPI CSI-2 RX subsystem? 
3. How should I right shift the image without losing the framerate?

Here are my reg dumps with desciption

width=1920, height=1080, fmt.code=0x300f
CSR and HC register dump, mipi csi0

HC num of lanes	[0x100]	0x00000001	2 Lanes
HC dis lanes	[0x104]	0x0000000c	Disable Lane 2 + 3
HC BIT ERR	[0x108]	0x00000000	No Errors
HC IRQ STATUS	[0x10c]	0x00000008	ULPS status change
HC IRQ MASK	[0x110]	0x000001FF	All Interrups active
HC ULPS STATUS	[0x114]	0x00000000	No status state active
HC DPHY ErrSotHS	[0x118]	0x00000000
HC DPHY ErrSotSync	[0x11c]	0x00000000
HC DPHY ErrEsc	[0x120]	0x00000000
HC DPHY ErrSyncEsc	[0x124]	0x00000000
HC DPHY ErrControl	[0x128]	0x00000000
HC DISABLE_PAYLOAD	[0x12c]	0x00000000	No payload disabled
HC DISABLE_PAYLOAD	[0x130]	0x00000000	No payload disabled
HC IGNORE_VC	[0x180]	0x00000000	Virtual channel active
HC VID_VC	[0x184]	0x00000000	0 virtual channels expected
HC FIFO_SEND_LEVEL	[0x188]	0x00000000
HC VID_VSYNC	[0x18c]	0x00000000
HC VID_SYNC_FP	[0x190]	0x00000000
HC VID_HSYNC	[0x194]	0x00000000
HC VID_HSYNC_BP	[0x198]	0x00000000	CSR and HC register dump, mipi csi0
CSR PLM_CTRL	[0x000]	0x00000801	VALID_OVERRIDE = 1 ENABLE = 1
CSR PHY_CTRL	[0x004]	0x0020007F	RTERM_SEL = 1 S_PRG_RXHS_SETTLE = 7 CONT_CLK_MODE = 1 DDRCLK_EN = 1 AUTO_PD_EN = 1 RX_ENABLE = 1
CSR PHY_Status	[0x008]	0x00000001	LANES_STOPPED = 1
CSR PHY_Test_Status	[0x010]	0x00000000
CSR PHY_Test_Status	[0x014]	0x00000000
CSR PHY_Test_Status	[0x018]	0x00000000
CSR PHY_Test_Status	[0x01c]	0x00000000
CSR PHY_Test_Status	[0x020]	0x00000000
CSR VC Interlaced	[0x030]	0x00000000	No virtual channel is interlaced
CSR Data Type Dis	[0x038]	0x00000000
CSR 420 1st type	[0x040]	0x00000000
CSR Ctr_Ck_Rst_Ctr	[0x044]	0x00000001	CTL_CLK_OFF = 1
CSR Stream Fencing	[0x048]	0x00000000	No virtual channel is fenced (RW - to Pixelformater)
CSR Stream Fencing	[0x04c]	0x00000000	No virtual channel is fenced (RO - from Pixelformater)

CHNL_CTRL	[0x00]	0xE0FF0002	CHNL_EN = 1 CLK_EN = 1 CHNL_BYPASS = 1 SEC_LB_src=0 src=2 (MIPI)
CHNL_IMG_CTRL	[0x04]	0x0F000001	FORMAT = RAW16 GBL_ALPHA_VAL = 0 GBL_ALPHA_EN = 0 DEINT = 0 DEC_X = 0 DEC_Y = 0 CROP_EN = 0 VFLIP_EN = 0 HFLIP_EN = 0 YCBCR_MODE = 0 CSC_MODE = 0 CSC_BYP = 1
CHNL_OUT_BUF_CTRL	[0x08]	0x00000092	LOAD_BUF1_ADDR = 0 LOAD_BUF2_ADDR = 0 PANIC_SET_THD_Y = PANIC > 12,5% OUT BUF
CHNL_IMG_CFG	[0x0c]	0x04380780	HEIGHT = 1080 WIDTH = 1920
CHNL_IER	[0x10]	0x3DFF0000	FRM_RCVD_EN = 1 AXI_WR_ERR_V_EN = 1 ... ALL IRQs EN = 1
CHNL_STS	[0x14]	0x00000200	LINE_STRD = 0 FRM_STRD = 0, AXI_WR_ERR_U = 0 ... PANIC_V_BUF = 0 OFLW_V_BUF = 0 ... BUF1_ACTIVE = 1 BUF2_ACTIVE = 1
CHNL_SCL_IMG_CFG	[0x98]	0x04380780	HEIGHT = 1080 WIDTH = 1920
CHNL_SCALE_FACTOR	[0x18]	0x10001000	Y_SCALE = 1.0 X_SCALE = 1.0
CHNL_SCALE_OFFSET	[0x1c]	0x00000000	Y_OFFSET = 0.0 X_OFFSET = 0.0
CHNL_CROP_ULC	[0x20]	0x00000000	X = 0 Y = 0
CHNL_CROP_LRC	[0x24]	0x00000000	X = 0 Y = 0
CHNL_CSC_COEFF0 CHNL_CSC_COEFF1 CHNL_CSC_COEFF2 CHNL_CSC_COEFF3 CHNL_CSC_COEFF4 CHNL_CSC_COEFF5	[0x28] [0x2c] [0x30] [0x34] [0x38] [0x3c]	0x00000000
CHNL_ROI_0_ALPHA	[0x40]	0x00000000	ALPHA = 0 ALPHA_EN = 0
CHNL_ROI_0_ULC CHNL_ROI_0_LRC	[0x44]	0x00000000	X = 0 Y = 0
...
CHNL_OUT_BUF1_ADDR_Y	[0x70]	0xA7000000
CHNL_OUT_BUF1_ADDR_U	[0x74]	0x00000000	Not used in one plane operation
CHNL_OUT_BUF1_ADDR_V	[0x78]	0x00000000	Not used in one or two plane operation
CHNL_OUT_BUF2_ADDR_Y	[0x8c]	0xA6400000
CHNL_OUT_BUF2_ADDR_U	[0x90]	0x00000000	Not used in one plane operation
CHNL_OUT_BUF2_ADDR_V	[0x94]	0x00000000	Not used in one or two plane operation
CHNL_OUT_BUF_PITCH	[0x7c]	0x00000F00	LINE_PITCH = 3840
CHNL_IN_BUF_ADDR	[0x80]	0x00000000	RESERVED
CHNL_IN_BUF_PITCH	[0x84]	0x00000000	RESERVED
CHNL_MEM_RD_CTRL	[0x88]	0x00000000	RESERVED

[mallibeerala]

Hi,

I am using RGB888 format, Image is displaying in HDMI port but strips are adding in image, I am thinking some bits are missing. Please help us to resolve this Issue. I am getting Image as below.

Thanks & Regards,
Mallikarjuna B.

[mz-fixposition]

@Bio_TICFSL 
I am experiencing the same issue

Do you have any update on this issue with the CSI-2 data formats layer?

[pmliquify]

Hi mz-fixposition,

up to now I don't have a perfect solution. If you correct the 4 bit shift while debayering the image you don't lose any framerate.

[Dharanitharan]

Hi pmliquify,

I am trying to stream Monochrome camera Y10 in imx8qm facing the same issue like you. The Y10 data is left shifted by 4. did you had any solution for this?

Please help me if you have any.

Thanks and regards

[wasim_nazir]

I think there is some confusion in the TRM(REV-E): i.MX 8DualX/8DualXPlus/8QuadXPlus Applications Processor Reference Manual

Statement 1:

The CSI data is right LSB aligned and zero padded depending
on data format. When interfacing ISI, CSI data is shifted 6-bits
due to ISI bits [5:0] always being zero
(0bxxCSIDATAxxxxxx). All RAW14, RAW12, RAW10,
RAW8, and RAW6 video data is filled from BIT[13] to LSB,
the remaining bits are zero padded. Only RAW16 input data
will be saved to memory from BIT[15] to LSB.

Statement 2:

001100b - RAW10 - 10-bit RAW data packed into 16-bit WORD with 6 LSBs waste bits

Found that statement 1 doesn't matches with statement 2.

[Bio_TICFSL]

Hello wasim,

Supported cameras and formats are described in AN12187 Quick Start Guide

for MINISASTOCSI for i.MX 8M Evaluation Kit

https://www.nxp.com/docs/en/application-note/AN12187.pdf 

It support raw10, t1he clocks are MIPI CSI host clocks, they are not related to external camera input signal.

The host can support 1, 2,3 and 4 lanes camera, so 1 lane camera can be supported. The lane number is set from device tree, "data-lanes = <1 2>;" means 2 lanes are used:

&mipi_csi_1 {
 #address-cells = <1>;
 #size-cells = <0>;
 status = "okay";
 port {
  mipi1_sensor_ep: endpoint1 {
   remote-endpoint = <&ov5640_mipi1_ep>;
   data-lanes = <1 2>;
  };

  csi1_mipi_ep: endpoint2 {
   remote-endpoint = <&csi1_ep>;
  };
 };
};

[wasim_nazir]

Hi BioTICFSL,

Thanks for your reply.

Our SOC is 8QXP MEK and not 8M.

I have tried for both single lane and multi-lane. Our endpoint supports 2 lanes.

Any idea on the documentation of CSI2 Subsystem CSR registers.

Thanks

[wasim_nazir]

We tried using single data-lane but still the same issue.

Can anyone help?