RAM configuration in imx6ul barebox

[ganesh_k]

Hello everyone,

barebox version:2017.04.0

RAM: MT41K512M8DA-107P

         we are doing flat designing the board with imx6ul SOC. with two RAMs(MT41K512M8DA-107P). can anyone please share the procedure to configure the 2 RAMs to make it as 1GB in the barebox level.previously we have the configuration for 512MB with single RAM(MT41K128M16JT-125 IT). what are the modifications needed to configure this as 1GB RAM.

Thanks & Regards

Ganesh.K

[igorpadykov]

Hi Ganesh

for new memory it is necessary to run ddr test (also use i.MX6ULL_LPDDR2_Script_Aid )

i.MX6/7 DDR Stress Test Tool V3.00 

and update uboot *.cfg file with new ddr calibration coefficients found from test

mx6ul_14x14_evk\freescale\board - uboot-imx - i.MX U-Boot 

then adjust uboot #define PHYS_SDRAM_SIZE in

mx6ul_14x14_evk.h\configs\include - uboot-imx - i.MX U-Boot 

Best regards
igor
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[ondrat]

Hello @igorpadykov,

I've run "DDR_Stress_tester_v3.00" for imx6 dual core based SoM with 2GB RAM, just to play with this tool. I've got different results on each run. Is it expectable behaviour or what it could mean?

Target: MX6DQ, DDR Freq: 528 Mhz, ...

Example results:

#1 ------------------------------------------------------------------------

...

MMDC registers updated from calibration

Write leveling calibration
MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x00240022
MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x002F0029
MMDC_MPWLDECTRL0 ch1 (0x021b480c) = 0x001B002D
MMDC_MPWLDECTRL1 ch1 (0x021b4810) = 0x000E0021

Read DQS Gating calibration
MPDGCTRL0 PHY0 (0x021b083c) = 0x43200330
MPDGCTRL1 PHY0 (0x021b0840) = 0x03180314
MPDGCTRL0 PHY1 (0x021b483c) = 0x431C032C
MPDGCTRL1 PHY1 (0x021b4840) = 0x03180258

Read calibration
MPRDDLCTL PHY0 (0x021b0848) = 0x42363A3C
MPRDDLCTL PHY1 (0x021b4848) = 0x3A3A3444

Write calibration
MPWRDLCTL PHY0 (0x021b0850) = 0x383C3E3A
MPWRDLCTL PHY1 (0x021b4850) = 0x3E32423C

Success: DDR calibration completed!!!

#2 ------------------------------------------------------------------------

...

MMDC registers updated from calibration

Write leveling calibration
MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x00240022
MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x002F0029
MMDC_MPWLDECTRL0 ch1 (0x021b480c) = 0x001B002D
MMDC_MPWLDECTRL1 ch1 (0x021b4810) = 0x000E0021

Read DQS Gating calibration
MPDGCTRL0 PHY0 (0x021b083c) = 0x431C032C
MPDGCTRL1 PHY0 (0x021b0840) = 0x03180310
MPDGCTRL0 PHY1 (0x021b483c) = 0x431C0330
MPDGCTRL1 PHY1 (0x021b4840) = 0x03180258

Read calibration
MPRDDLCTL PHY0 (0x021b0848) = 0x42363E3C
MPRDDLCTL PHY1 (0x021b4848) = 0x3A3A3642

Write calibration
MPWRDLCTL PHY0 (0x021b0850) = 0x383C3E3A
MPWRDLCTL PHY1 (0x021b4850) = 0x4032423C

Success: DDR calibration completed!!!