Hi all,
I have a trouble with pin "hogging" in a particular case, and no explanation about it.
I have a camera chip connected to an imx6q through spi. The chip needs 4 gpios to work (GPIO2_28, GPIO3_19, GPIO3_20 and GPIO5_0). All these gpio are named in ecspi2 structure, and pin are declared in pinctrl_gschip.
For me, it would be enough to make the chip work... But it's not the case, since the GPIO2_28, set up in the chip driver, has no level change at all.
To make it work, i have to also declare the pin in iomuxc structure. In this case, the GPIO2_28 is fully operationnal.
Do you see some explanation about this issue ?
&ecspi2 {
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio2 26 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
status = "okay";
gschip: gschip@0 {
compatible = "gn,gschip";
reg = <0>;
pinctrl-0 = <&pinctrl_gschip>;
mclk = <74500000>;
mclk_src = <0>;
ipu= <0>;
csi = <0>;
spi-max-frequency = <20000000>;
reset-gpio = <&gpio2 28 0>;
sdi_lock-gpio = <&gpio3 19 0>;
rate_det-gpio = <&gpio3 20 0>;
data_err-gpio = <&gpio5 0 0>;
};
};
pinctrl_gschip: gschipgrp {
fsl,pins = <
MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b1
MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b1
MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b1
MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b1
>;
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
imx6qdl-starlitehd {
pinctrl_hog: hoggrp {
fsl,pins = <
MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b1 /* Reset Gennum */
>;
};
Best regards,
Christophe