Hello,
1.
On the EVK scheme :
VDD_ARM_SOC_IN is controlled by DCDC_3V3_PG (3.3V is good),
but VDD_HIGH_IN is connected directly to DCDC_3V3. This means :
VDD_SOC_IN is ramping up when VDD_HIGH_IN is not higher than 3.0 V.
VDD_SOC_IN is ramping down when VDD_HIGH_IN is lower than 3.0 V.
VDD_SOC_IN is not ramping down earlier than VDD_HIGH_IN.
So, the EVK should not be affected with the erratum. But the Errata recommends the following :
The workarounds below should be both used to avoid SNVS_LP registers reset issue:
• VDD_HIGH_IN power down is earlier than VDD_SOC_IN.
• VDD_HIGH_IN voltage power is less than or equal to 3.0 V.
The second item is not satisfied on the EVK.
2.
All registers inside SNVS_LP may be reset. Please look at section 46.7.1 (SNVS Memory Map) of i.MX 6UltraLite Applications Processor Reference Manual, Rev. 1, 04/2016.
Have a great day,
Yuri
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