Question, i.MX6SL boot setting

[Aemj]

Dear NXP team,

I would like to ask about the boot setting for i.MX6SL eMMC boot.

My customer wants to realize the fast boot on i.MX6SL system.

The customer thought that it is possible to realize fast boot from eMMC by configure DIPSW 1-4 on i.MX6SL-EVK board.

But after setting the DIPSW1-4, the boot from eMMC hanged.

And they found the following discussion in i.MX community.

https://community.nxp.com/thread/354655

After reading the community thread, they think that ‘fast boot’ from eMMC can not be realized even when they configure

They think the fast boot is available only when SD boot.

DIPSW1-4. And configuring EXT_CSD[179] seems to be needed for eMMC fast boot.

Is the above understanding correct?

Thanks,

Miyamoto

[igorpadykov]

Hi Miyamoto

>They think the fast boot is available only when SD boot.

right, as described in RM:

>DIPSW1-4. And configuring EXT_CSD[179] seems to be needed for eMMC fast boot.

>Is the above understanding correct?

yes this is correct understanding, links below may be useful

imx6q, eMMC fast boot

imx6q eMMC Fast Boot, someone using it can help ?

Best regards

igor

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[Aemj]

Hi Igor,

Thanks for your reply.

We found the following written in RM at ‘Table 8-13. MMC and eMMC Boot Details’.

“This mode can be selected by BOOT_CFG1[4](Fast Boot) fuse.”

Should user set BOOT_CFG1[4] into ON(1) not only for SD fast boot but also for eMMC fast boot?

And in the Table8-13, the following written is seen. (Under the blue line.)

“BOOT ACK is selected by BOOT_CFG2[1].”

The BOOT_CFG2[1] is described in Table5-5 as ‘Fast boot Acknowledge disable’.

We believe that BOOT_CFG2[1] written in Table8-13 is typo and the correct is BOOT_CFG1[2].

Correct?

Could you show me the exact setting for the following condition?

======= the condition ========

　[User Partition] enabled for boot.

　 Fast boot acknowledgement: [Enabled]

　 Fast boot bus width: [8 bit]

　 DDR boot mode: [Enabled]

　 [Retain] boot bus width settings.

　EXT_CSD[179] = 0x78

　EXT_CSD[177] = 0x16

======== end of the condition ========

======== the settings ========

　　　BOOT_CFG1[7:0] = 011? ??00

　　　BOOT_CFG2[7:0] = 1100 10?0

　　　BOOT_CFG3[7:0] = 0000 0000

EXT_CSD[179] = 0x??  (if change from 0x78 is needed)

EXT_CSD[177] = 0x??  (if change from 0x16 is needed)

===========================

Best Regards,

Miyamoto

[igorpadykov]

Hi Miyamoto

>Should user set BOOT_CFG1[4] into ON(1) not only for SD fast boot but also for eMMC fast boot?

yes, also for eMMC fast boot

>We believe that BOOT_CFG2[1] written in Table8-13 is typo and the correct is BOOT_CFG1[2].

>Correct?

yes

>Could you show me the exact setting for the following condition?

======== the settings ========

BOOT_CFG1[7:0] = 011? ??00   <---  0111 0000

BOOT_CFG2[7:0] = 1100 10?0   <--- bit setting depends on used volage

BOOT_CFG3[7:0] = 0000 0000

Best regards

igor

[SLICE]

Hi Igor,

Thanks so much for your answer.

We found the following threads on i.MX community.

     https://community.nxp.com/message/808909

     https://community.nxp.com/thread/351590

     https://community.nxp.com/thread/354655

And in all the above threads, they said that i.MX6SX cannot boot-up from eMMC when BOOT_CFG1[4] = ON in their experience.

And in conclusion, all of the threads are concluded with “BOOT_CFG1[4] should be OFF for boot-up from eMMC”.

Then, it seems that your comment, BOOT_CFG1[7:0] <= 0111 0000, and the threads do not match.

Could you give your comment on that?

BR,

Miyamoto

[igorpadykov]

Hi Miyamoto

sorry, I can not comment on other therads.

Regarding “BOOT_CFG1[4] description RM is correct, also I checked

i.MX6SL ROM sources, it uses BOOT_CFG1[4] during eMMC fast boot.

Please create new thread with detailed problem description,

if you have issues with eMMC boot.

In particular what processor you are speaking: SL or SX,

first question was about SL, last update for SX.

Best regards

igor

[Aemj]

Hi Igor,

> Please create new thread with detailed problem description,

OK, I will create.

> In particular what processor you are speaking: SL or SX,

> first question was about SL, last update for SX.

Sorry, I missed. It's SL.

Thanks,

Miyamoto