Processor Expert for i.MX Processors (Ver 1.1.0)

[keitanagashima]

Dear All,

Hello. I tried to use the Processor Expert for i.MX Processors (Ver 1.1.0).

My steps is below.

1. Select File > New > Processor Expert Project, from the IDE menu bar.

2. Select the "Boards" as "i.MX6Q_Smart_Device_RevB".

[Q1]

Refer to "Functional Properties" Tab in the Component Inspector View.

I referred DDR_SEL setting of DRAM pins.

DDR_SEL = LPDDR2 mode

Does this component reflect the setting of MCIMX6Q-SDP?

[Q2]

Refer to ECSPI of "Routing" Tab in the Component Inspector View.

"Power Group" was not reflected Power Group's name.

But, "Figure 17. Expanded view mode" in Getting_Started_with_PEx_for_iMX.pdf was reflected the Power Group's name.

Does it need any setting to reflect the Power Group's name?

Best Regards,

Keita

[Yuri]

1.

For i.MX6 SDP / SDB, DDR_SEL bit filed should be set as DDR3.

Nevertheless, it is possible to vary DDR_SEL options, since DDR_SEL

is intended to provide ‘fine tuning’ of DRAM signals.

2.
It is needed to select pin functionality (User Pin/Signal Name) in order

to reflect the Power Group's name.

Have a great day,
Yuri

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

[keitanagashima]

Dear Yuri,

Hello.

1.

I dumped the Pad Group Control Register (IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE) with MCIMX6Q-SDP + Linux L3.14.28_1.0.0.

DDR_SEL bit was "11" (=DDR3— DDR3 mode )

But, the this component (IOMUX tool) didn't reflected the MCIMX6Q-SDP's parameters.

Does this component reflect the setting of MCIMX6Q-SDP(Linux or Android)?

2.

Refer to below picture.

It have already checked the pin function.

But, Power Group's name was not changed.

Best Regards,

Keita

[PetrZeman · Accepted solution]

hello Keita,

I've checked the default configuration we've used for Sabre boards within PEx for i.MX and compared to what we have in data for the board configuration that we got from the previous IOMUX tool and there're really set DDR_SEL fields to default 0b10 = LPDDR2 mode although it does make sense to set this field to 0b11 = DDR3 mode because the boards have DDR3 modules.

I'm not sure if this particular setting has been done for some reasons of tweaking DDR signals on the board, I haven't confirmed this yet. We'll continue investigation on this and eventually will fix the default DDR_SEL fields for the Sabre boards.

To address your second question, it seems like a bug on the Expanded view mode.. as a workaround, you can switch to Collapsed and you will see the power group name and actual voltage level for selected pin function on this tab instead of expanded view. We'll also follow up with this bug, I'll update you with the status.

Thanks and regards,

Petr Zeman

Processor Expert SW Development Engineer

[keitanagashima]

Hello. Petr,

Thank you for your reply.

OK. I got it.

If some bugs are fixed, it is useful tool to support a customer!

Best Regards,

Keita