Problem in configuring USDHC-2 and USDHC-3 with different frequencies

[asmitaamonkar1]

Hi,
Linux BSP version : 4.1
CPU : imx6 quad
Purpose: To configure the usdhc-2 with 48 Mhz and usdhc-3 with 42 Mhz

To obtain the change in frequencies following registers are configured:

1. PLL_PFD2 frequency is set to 339MHz: Configuration:
CCM_ANALOG_PFD_528n (Address: 0x20c8100)with divisor value : 0X1c1c19 (PFD2 divisor : 28) (528*18/28 = 339 Mhz)

2. CSCDR1(Address: 0x20c4024): 0x007E0B00; ( Changed usdhc3_podf divisor to 8, and usdhc2_podf divisor to 7)

3. CSCMR1(Address: 0x20c401C):0x00900000; (usdhc2_clk_sel set to 0 , usdhc2_clk_sel set to 0- selected derive clock from 396M PFD option)

4. CCM_CCGR6(Address: 0x20c4080)- value is set as 0xC30
5. CCM_CMEOR(Address: 0x20c4088)- value is 0x7FFFFFFF

With this configuration it was expected to change, usdhc-2 clock frequency to 48Mhz and usdhc-3 clock frequency to 42 Mhz. However, it was observed that usdhc-2 and usdhc-3 both clock frequencies are configured to 48 MHz.

It would be highly appreciated if any one can help understand the root cause of the problem or let me know if any of the configurations are missing.

Help needed urgently.

Regards,
Asmita

[igorpadykov]

Hi Asmita

for verifying linux settings please attach jtag and check with

oscilloscope usdhc-2 and usdhc-3 clocks on CCM_CLKO1(2)

pad using CCM_CCOSR register, described in sect.18.6.21 CCM Clock Output

Source Register (CCM_CCOSR) i.MX6DQ Reference Manual

http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6DQRM.pdf

Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

[asmitaamonkar1]

Hi Igor,

Thanks for the reply. We are trying to measure the clock as mentioned .

Furthermore, wanted to know the meaning of following : ( Page 813 of the reference manual)

Does this mean that usdhc1_clk_root will be used to generate clock for USDHC-2 and USDHC-3 as well?

Please help understand above table.

How to use usdhc3_clk_root to generate usdhc-3 clock ?

We understand from this figure that usdhc3_clk_root can be used to generate clock for usdhc-3. Please confirm our understanding

Thanks in advance.

Regards,

Asmita

[igorpadykov]

Hi Asmita

could you clarify your question, as on page 813

http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6DQRM.pdf 

there is nothing to understand it.

Best regards
igor

[asmitaamonkar1]

Hi Igor,

Sorry It is page Number 807 in the reference manual link.

1.My basic problem is, when I check the clock on SD2_CLK(USDHC-2) and SD3_CLK(USDHC-3) using oscilloscope I can see only 48 MHz on both the clocks.

2. It is also observed that whatever clock I set on SD2_CLK(USDHC-2) , the same clock is observed on SD3_CLK( USDHC-3)

So I wanted to understand the table( page 807 the snapshots given in previous mail), that is there any settings because of which SD2_CLK is seen on the SD3_CLK pin also.

I have already shared the configuration, do you see any problem in those configurations ?

Please let me know if you need any further inputs.

Thanks & regards,

Asmita

[igorpadykov]

Hi Asmita

I checked above configuration, do not see any problem in it.

Page Number 807 is not useful for understnading USDHC clocks,

please use Figure 18-2. Clock Tree - Part 1   p.796,

select appropriate USDHC1(2,3,4)_CLK_ROOT clock and check its value observing

on CCM_CLKO1(2) pad using CCM_CCOSR register, described in sect.18.6.21

CCM Clock Output Source Register (CCM_CCOSR)

Best regards
igor

[asmitaamonkar1]

Hi Igor,

1. Checked USDHC2_CLK_ROOT on CCM_CLKO2 and observed that it’s clock as 48 MHz on NANDF_CS2 pin (which is as expected)

2. Checked USDHC3_CLK_ROOT on CCM_CLKO2 and observed that clock is not coming on the NANDF_CS2 pin ( remains high… )

3. We also checked the OSC_CLK which was observed as 24MHz ( As expected)

Are read/write operations required on USDHC-3 to check the clock ? or there could be some other problem.

One more observation, when CCM_CCOSR register values are changed through application, it gets changed only once . For checking another root clock, I have to reboot the board and again change the value of root clock to be checked.

Thanks & Regards,

Asmita