Power up/down sequence

[sapirbuz]

Hi,

[joanxie]

I don't know what board you are talking about, but you can refer to the data sheet to get information

[sapirbuz]

Hi,

For MIMXRT1051CVL5B, can you please review my low-level power architecture (picture below) to the NXP to verify I didn't miss something?

Are there any power up/down requirements besides that the VDD_SNVS_IN should power up first?

Are there any timing requirements that I miss in the datasheet?

[kerryzhou]

Hi @sapirbuz ,

   About the RT1050 power up and power down sequence, please refer to this document:

https://www.nxp.com/webapp/Download?colCode=MIMXRT105060HDUG&location=null

datasheet also has some information:

Wish it helps you!

Best Regards,

kerry

[sapirbuz]

Hi,

My architecture is described in the picture below:

It means that the SNVS_IN will be the first to turn off. 

Will the following architecture solve that problem?:

[kerryzhou]

Hi @sapirbuz ,

  From the requirement:

• Power Up Sequence Requirement
— VDD_SNVS_IN supply must be turned on before any other power supply or be connected (shorted) with VDD_HIGH_IN supply

• Power Down Sequence Requirement
— VDD_SNVS_IN supply must be turned off after any other power supply or be connected (shorted) with VDD_HIGH_IN supply

You can connect it together.

If you have any other questions, welcome to create the new question post, thanks, as this post already opened for more than one month.

Best Regards,

Kerry

[sapirbuz]

Thank you!

So when I connect those pins together, the power up/down sequence rules are canceled and I can power up/down in the sequence I want?

[kerryzhou]

Hi @sapirbuz ,

The above sequence not canceled, just  VDD_SNVS_IN and VDD_HIGH_IN can be together.

Other sequence still need to follow.

Best Regards,

Kerry