Power supply failure mode.

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Power supply failure mode.

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takashitakahash
Contributor III

Would you please present the FMEA about if only out of the power supply to the iMX6 1 strains unbootable due to power failure.

Specifically, do not supplied just below power line.

Or lower operating voltage range .

Please tell me failure modes of i.MX6.

VDDARM_IN

VDDARM23_IN (if the Quad Core)

VDDSOC_IN

VDDHIGH_IN

NVCC_DRAM

DRAM_VREF

NVCC_EIM0-2

If I assert a POR_B, when a fault occurs in the part of the power of the above failures occur?

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igorpadykov
NXP Employee
NXP Employee

Hi Takashi

processor will not boot if any of these power supplies

(except DRAM_VREF) will not have proper voltages, as

this is required by power - up sequence. When POR is deasserted

all power supplies and clocks should be applied according to datasheet

requirements. I think some kind of failure analysis can be found in

Chapter 8 "Avoiding Board Bring-up Problems"

i.MX6 System Development User’s Guide (rev.1, 6/2013)

http://cache.freescale.com/files/32bit/doc/user_guide/IMX6DQ6SDLHDG.pdf

Best regards

igor

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igorpadykov
NXP Employee
NXP Employee

Hi Takashi

processor will not boot if any of these power supplies

(except DRAM_VREF) will not have proper voltages, as

this is required by power - up sequence. When POR is deasserted

all power supplies and clocks should be applied according to datasheet

requirements. I think some kind of failure analysis can be found in

Chapter 8 "Avoiding Board Bring-up Problems"

i.MX6 System Development User’s Guide (rev.1, 6/2013)

http://cache.freescale.com/files/32bit/doc/user_guide/IMX6DQ6SDLHDG.pdf

Best regards

igor

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Note: If this post answers your question, please click the Correct Answer button. Thank you!

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