Normally the DDR clock are sourced via PLL2 – PFD2 and this source passes the PRE_PERIPH mux. The question is how the sub CCM register CCM_CBCMR are naming this mux. The pre_periph2 seams [22:21] to correspond to PFD2 but the question if it or pre_periph [19:18] should be used instead or both??
The pre_periph2 in CCM_CBCMR[22:21] is to select clock source for periph2_clk, it is for mmdc_ch1_axi_clk_root, the pre_periph in CCM_CBCMR[19:18] is to select clock source for periph_clk, and mmdc_ch0_axi_clk_root is sourcing from periph_clk, you can refer to the clock tree in i.MX6Q RM Figure 18-5 in CCM chapter. These are two different clock mux for different clock path.