PCIe 32bit bus master transfers

[zerocom38]

I have a PCIe device (which is an FPGA board) connected to the i.MX 8M and I see a problem with DMA transfers. The device itself works well for a couple of years on older ARM systems. Here is my problem:

I started a DMA transfer of 4 bytes on the PCI bus (the DMA controller is inside the device so that it will do a PCI bus master transfer) and this transfer never started or finished, so it looks like the transfer size of 4 bytes is too small. Larger transfers (8 or more bytes) work fine.

Is there a limitation on the i.MX 8 which disallows 32bit transfers? Is there a way to change/configure it to allow 32bit DMA transfers or could this be something else? Any help is appreciated.

I'm using a Linux kernel 5.4.70-2.3.0 right now, which comes with an iWave Q7 module.

[zerocom38]

Hello @Sanket_Parekh,

I don't use the embedded DMA controller, instead, I use the DMA controller from the PCIe device. A 4-byte DMA transfer doesn't work, which lets me think that only 64-bit (bus master) transfers are possible. Is this true or is there an option to configure/change that?

Regards
Stefan

[Sanket_Parekh]

Hello @zerocom38 

I hope you are doing well.

->Yes, It is true DMA controller on the imx8m only supports 8-byte transfers, because it uses a 4-byte wide data path, so it won't be able to perform 4-byte transfers.
->The SDMA system bus supports a 32-bit data path and a 16-bit address bus. The system bus datapath is used for both 16-bit instruction (program) memory access and 32-bit data access.
->DMA units interface to the core via the Functional Unit Bus and use dedicated registers to perform DMA transfers.

->Please refer to section 7.2 SDMA for more details.
->Please refer to the diagram 7.2.1.1 Block Diagram for detail.
https://www.nxp.com/webapp/Download?colCode=IMX8MDQLQRM

I hope this information helps!

Thanks & Regards,

Sanket Parekh

[Sanket_Parekh]

Hello @zerocom38 

I hope you are doing well.

->PCIe interface that has some features.
• Embedded DMA
->The Data Base Interface can access all 4096 bytes (1024 DWORDs) of the PCI Express configuration space per function. DBI can also access iATU and DMA configuration space.
->PCIe address bus can be set as either 32/64 bits.
->To start a DMA transfer one has to make sure the size of the DMA transfer is set correctly.
->Please refer to section - DMA Transfer Size Register in the RM.
->One can also find the details regarding how to detect whether the DMA transfer is completed or not.
->The peripheral(PCIE) can easily "stream" the data from (or to) an internal register that's one word long(PCIe payload size)(32b/64b),
->One can also check the same thing with the latest kernel, Please make sure to use that as it is recommended to use the latest driver and firmware to avoid such kind of issue.

I hope this information helps!

Thanks & Regards,

Sanket Parekh