I'm using an iMX53 and I have designed for two DDR3 chips of 2Gb (128M-bit x 16) giving a total of 512MBytes of RAM.
My question is on how to lay out the PCB.
The CPU has the ability to do read and write leveling which means I can use a "fly-by" topology. But, because i'm using only two RAM chips i'm thinking that it would be far easier to use a balanced line or tree type topology that i would use on DDR2.
What would you advise?
You need to go to:
and there in "PRINTED CIRCUIT BOARDS AND SCHEMATICS..." you will find the links to get the files once you login with your user.
Hope this can help you.
I found a section in the document "MX53UG.pdf" which says exactly what you said.
What I haven't been able to find is an example layout for the QSB. Do you know if one is available?
My recommendation will be to use the T Configuration, you do not need to adjust the delay of the byte groups later and is more easily balance as you explain, you can get as a reference the 53QSB board available in the freescale to take it as an example how to route your DDR.