Optional LDO in i.MX6QSDP schematic

[torus1000]

Dear chip experts,

According to the SPF-27392_C4.pdf schematics, I tried to replace VGEN5 supply with optional LDO.

This LDO meets the additional current requirement but I worry about the startup timing.

- Is there any timing restrictions for LDO startup like VGEN5 startup sequece?
- If yes, in order to meet the timing, is it OK to input VGEN5 to the LDO pin5(SHDN*) instead of SYS_4V2?
- Does this option circuit already comfirmed and it worked if  R32(0 ohrm) mounted ?

Can anybody help me?

Thanks.

[Yuri · Accepted solution]

Hello !

  You may use the Optional LDO solution to supply both VDDHIGH_IN and VDD_SNVS_IN

of the i.MX6. On the scheme only VDD_SNVS_IN is provided by the LDO,  “the optional LDO U9

shown on this page could be reconfigured to supply both VDDHIGH_IN and VDD_SNVS_IN”.
In such case there are no power sequence violation, assuming VDDHIGH_IN and VDD_SNVS_IN

turned on first.

Have a great day,
Yuri

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