Openocd on the imx6ULL EVK

[iancaddy]

Hi All,

We designed a custom board using an imx6ULL processor, and I have been trying to get openocd (using a Olimex ARM-USB-TINY-H) to work with it, but I get so far, and then it stops.

We then purchased a imx6ULL EVK assuming there might be something wrong with our custom board, but it has the same / similar issues.

I have got it to a state where it looks like it is starting up OK, but I can not halt or reset the EVK.  Note there is no firmware programming into the EVK (the microSD card is out).  I am happy to provide my exisitng imx6ull.cfg and openocd.cfg files if anyone is interested.  This is the output I am getting:

Open On-Chip Debugger 0.10.0
Licensed under GNU GPL v2
For bug reports, read
    http://openocd.org/doc/doxygen/bugs.html
Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'.
Warn : imx6.sdma: nonstandard IR value
adapter speed: 1000 kHz
trst_and_srst separate srst_gates_jtag trst_open_drain srst_open_drain connect_deassert_srst
adapter speed: 1000 kHz
jtag_ntrst_delay: 1000
Info : clock speed 1000 kHz
Info : JTAG tap: imx6.dap tap/device found: 0x5ba00477 (mfg: 0x23b (ARM Ltd.), part: 0xba00, ver: 0x5)
Info : TAP imx6.sdma does not have IDCODE
Info : JTAG tap: imx6.sjc tap/device found: 0x088c101d (mfg: 0x00e (Freescale (Motorola)), part: 0x88c1, ver: 0x0)
Error: target->coreid 0 OSLock sticky, core not powered?

When turning on debug I get the following:

Info : 351 1185 core.c:959 jtag_examine_chain_display(): JTAG tap: imx6.sjc tap/device found: 0x088c101d (mfg: 0x00e (Freescale (Motorola)), part: 0x88c1, ver: 0x0)
Debug: 352 1185 core.c:1190 jtag_validate_ircapture(): IR capture validation scan
Debug: 353 1191 core.c:1248 jtag_validate_ircapture(): imx6.dap: IR capture 0x01
Debug: 354 1191 core.c:1248 jtag_validate_ircapture(): imx6.sdma: IR capture 0x00
Debug: 355 1191 core.c:1248 jtag_validate_ircapture(): imx6.sjc: IR capture 0x01
Debug: 356 1191 openocd.c:153 handle_init_command(): Examining targets...
Debug: 357 1191 target.c:1517 target_call_event_callbacks(): target event 21 (examine-start)
Debug: 358 1191 arm_adi_v5.c:603 dap_dp_init():  
Debug: 359 1203 arm_adi_v5.c:637 dap_dp_init(): DAP: wait CDBGPWRUPACK
Debug: 360 1203 arm_adi_v5.h:428 dap_dp_poll_register(): DAP: poll 4, mask 0x20000000, value 0x20000000
Debug: 361 1222 arm_adi_v5.c:644 dap_dp_init(): DAP: wait CSYSPWRUPACK
Debug: 362 1222 arm_adi_v5.h:428 dap_dp_poll_register(): DAP: poll 4, mask 0x80000000, value 0x80000000
Debug: 363 1274 arm_adi_v5.c:785 dap_find_ap(): Found APB-AP at AP index: 1 (IDR=0x44770002)
Debug: 364 1283 arm_adi_v5.c:712 mem_ap_init(): MEM_AP Packed Transfers: disabled
Debug: 365 1283 arm_adi_v5.c:723 mem_ap_init(): MEM_AP CFG: large data 0, long address 0, big-endian 0
Debug: 366 1294 arm_adi_v5.c:785 dap_find_ap(): Found AHB-AP at AP index: 0 (IDR=0x74770001)
Debug: 367 1303 arm_adi_v5.c:712 mem_ap_init(): MEM_AP Packed Transfers: enabled
Debug: 368 1303 arm_adi_v5.c:723 mem_ap_init(): MEM_AP CFG: large data 0, long address 0, big-endian 0
Debug: 369 1331 cortex_a.c:3007 cortex_a_examine_first(): didr = 0x3515f005
Debug: 370 1331 cortex_a.c:3008 cortex_a_examine_first(): cpuid = 0x410fc075
Debug: 371 1346 cortex_a.c:3017 cortex_a_examine_first(): target->coreid 0 DBGPRSR  0x2b
Debug: 372 1346 cortex_a.c:3026 cortex_a_examine_first(): target->coreid 0 was reset!
Debug: 373 1357 cortex_a.c:3033 cortex_a_examine_first(): target->coreid 0 DBGOSLSR 0xa
Debug: 374 1357 cortex_a.c:3039 cortex_a_examine_first(): target->coreid 0 OSLock set! Trying to unlock
Debug: 375 1388 cortex_a.c:3050 cortex_a_examine_first():    ret = 0, OSLSR = a
Error: 376 1388 cortex_a.c:3052 cortex_a_examine_first(): target->coreid 0 OSLock sticky, core not powered?
Debug: 377 1388 openocd.c:155 handle_init_command(): target examination failed

Note I have added some extra debug to the 0.10.0 log which is the return from trying to clear the OS Lock. and the DBGOSLSR regsiter is still the same.

Looking at the DBGPRSR it is showing 0x2B, which indicates (the bottom bit) that the core is powered, but I am still unable to unlock the OS Lock.

Does anyone have a working configuration file for this processor, or any hints about how I can get past this place?

regards,

Ian Caddy

[iancaddy · Accepted solution]

Hi All,

I appear to have this working now, and wanted to post the solution, although I am still a bit confused about it.

In my imx6ull.cfg file I based it on the original imx6.cfg file in the openocd tree but had to change the DAP address as it was incorrect for the imx6ULL part:

# core 0  -  0x82150000
# core 0  -  0x02130000
set _TARGETNAME $_CHIPNAME.cpu.0
target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap \
        -coreid 0 -dbgbase 0x02130000

Originally the DAP was setup to be 0x82150000 but looking through the im6ULL Reference Manual it shows the DAP to be at 0x02130000, and I could get DAP information at this address, but seems my write to clear the OSLock bit was failing (although the write said it worked OK, but did not change the value).

Looking through other imx configurations in the examples, I noticed that on the imx53.cfg file there was no DAP address loaded, so I thought maybe on a single core it was not needed, so I removed it:

set _TARGETNAME $_CHIPNAME.cpu.0
target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap

And the JTAG then tried to discover the DAP address from the ROM table:

Detected core 0 dbgbase: 80030000

Not anwhere near what the memory map in the reference manual indicates (in fact this address is somewhere int he DDR space).  Anyway, it is now working and I can halt the chip so I can start developing and debugging.  I have enclosed the imx6ull.cfg and openocd.cfg files I am currently using for reference, on the imx6ULL EVK.

imx6ull.cfg:

# Freescale i.MX6ULL processor
if { [info exists CHIPNAME] } {
   set  _CHIPNAME $CHIPNAME
} else {
   set  _CHIPNAME imx6
}
# CoreSight Debug Access Port
if { [info exists DAP_TAPID] } {
        set _DAP_TAPID $DAP_TAPID
} else {
        set _DAP_TAPID 0x5ba00477
}
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x0f \
        -expected-id $_DAP_TAPID
# SDMA / no IDCODE
jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x00 -irmask 0x0f

# System JTAG Controller
if { [info exists SJC_TAPID] } {
        set _SJC_TAPID $SJC_TAPID
} else {
        set _SJC_TAPID 0x088c101d
}

jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \
        -expected-id $_SJC_TAPID

# GDB target: Cortex-A7, using DAP, configuring only one core
set _TARGETNAME $_CHIPNAME.cpu.0
target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap

# some TCK cycles are required to activate the DEBUG power domain
jtag configure $_CHIPNAME.sjc -event post-reset "runtest 100"

proc imx6_dbginit {target} {
        # General Cortex-A8/A9 debug initialisation
        cortex_a dbginit
}

# Slow speed to be sure it will work
adapter_khz 1000
$_TARGETNAME configure -event reset-start { adapter_khz 1000 }
$_TARGETNAME configure -event reset-assert-post "imx6_dbginit $_TARGETNAME"
$_TARGETNAME configure -event gdb-attach { halt }

openocd.cfg file:

source ../openocd-0.10.0/tcl/interface/ftdi/olimex-arm-usb-tiny-h.cfg

# Setup information for our busblaster and imx6 solo
set DAP_TAPID 0x5ba00477
set SJC_TAPID 0x088c101d

# imx config
source imx6ull.cfg

# SRST connects to POR_B
#reset_config srst_only
#reset_config trst_and_srst srst_pulls_trst
#reset_config trst_and_srst separate trst_open_drain srst_open_drain
reset_config trst_and_srst trst_open_drain srst_open_drain

# No RTCK
adapter_khz 1000
#$_TARGETNAME configure -event reset-start { adapter_khz 1000 }

# Can't get watchdog to reset correctly yet.. for now, just don't reset here.
# We already did a reset back in init_reset anyway.
#$_TARGETNAME configure -event reset-assert {}

# This delay affects how soon after SRST we try to halt, so make it as
# small as possible. However, if it is too small we will fail the JTAG scan.
# Delay determined by experimentation
jtag_ntrst_delay 1000

gdb_port 3333
telnet_port 3000

Now to add in the DDR init and see if we can start debugging real code.

regards,

Ian Caddy

[igorpadykov]

Hi Ian

seems similar issue was reported on openocd mail list

OpenOCD - Open On-Chip Debugger / Mailing Lists 

One can try kernel boot parameter enable_wait_mode=off to disable

entering low power mode.

Best regards
igor
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[iancaddy]

Hi Igor,

Thanks for the reply, but unfortunately there is no firmware running on either board (except the ROM bootloader).  The EVK did not have the uSD card inserted.  Later in another test we put the uSD card in to see if the EVK was working correctly and it booted up OK.

When using OpenOCD with the Linux kernel in place, it stops (reboots) the kernel, but then allows the kernel to continue starting up after OpenOCD has finished initialiising.

We are also running a imx6ULL which seems to be different to the imx6UL.  I have also put this same question over on the OpenOCD mailing list, but so far have had zero interest in this issue.

regards,

Ian Caddy