Hi Igor,
I have seen this and DVFS is enabled as described in the document.
However the issue is that the min and max frequencies as shown by the proc file system are the same which suggests no frequency scaling can take place.
The min and max values seem to derive from a table in the file kernel_imx/arch/arm/mach-mx5/mx53_wp.c. There are a number of structures ( dvfs_wp and cpu_wp ) that seem to have a bearing on this but I have not been able to find a description of their usage. I've included the relevant ones that are being used for our board.
/* Place holder for dvfs_core setpoints for AEC parts */
static struct dvfs_wp dvfs_core_setpoint_aec[] = {
{33, 0, 33, 10, 10, 0x08} }; /*800MHz*/
/* working point for auto */
static struct cpu_wp cpu_wp_aec[] = {
{
.pll_rate = 800000000,
.cpu_rate = 800000000,
.pdf = 0,
.mfi = 8,
.mfd = 2,
.mfn = 1,
.cpu_podf = 0,
.cpu_voltage = 1100000,},
};
So can frequency scaling take place if the min and max frequency are the same? Is this determined by the structures shown above and, if so, how should these structures be used?
Thanks,
Bruno
