Need clarification on timing details of SEMC interface in i.MXRT

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Need clarification on timing details of SEMC interface in i.MXRT

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sowmiya_a
Contributor I

Hi,

We are using MIMXRT1024CAG4B in our design and we plan to interface an SDRAM to it.

1. As part of our timing analysis, we need to clarify how the microcontroller writes data to the SDRAM. Does it do so on the falling edge of the clock? can you confirm this detail.

2. Furthermore, we have noticed that the datasheet for the controller specifies a negative data output hold time of -1ns. Can you please explain the significance of this value? Does it imply that the hold time ends before the clock's falling edge? could you confirm if our understanding is correct?

sowmiya_a_0-1683698024742.png

 

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jingpan
NXP TechSupport
NXP TechSupport

Hi @sowmiya_a ,

1. Please see the timing diagram

jingpan_0-1683707541556.png

2. There is another explain diagram after the table.

jingpan_1-1683708586394.png

 

Regards,

Jing

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sowmiya_a
Contributor I

Hi,

Thanks for your assistance.

We have already taken the above mentioned timing diagrams into consideration and assumed that the microcontroller writes data into SDRAM in Clock's falling edge for our timing analysis. Can you confirm whether our assumption is accurate?

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jingpan
NXP TechSupport
NXP TechSupport

Hi @sowmiya_a ,

This screenshot is cut from W9812 SDRAM spec. Hope it can be helpful to you.

jingpan_0-1683857089574.png

 

Regards,

Jing

 

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