NAND Flash - encoding data with hardware ECC unit - generator polynomial

[simonlie]

Hello Community,

at the moment I'm working with an i.MX6 processor. Particularly I'm interested in NAND programming. I have the option to program a NAND Flash via boundary scan. Therefore I have to write software that encodes data with the ECC that is used by ROM Code. For example, if ROM Code ECC is set to BCH8, my software have to encode data with BCH8 too. Thus the ROM Code can read the data / ECC that is programmed to the NAND Flash.

To encode data with my software I need the generator polynomials that are used by the hardware ECC unit. Does somebody know the generator polynomials, that are used by the hardware ECC unit for BCH2 - 40 ?

If you would like any further information, please ask me.

Best regards,

Simon

[Yuri]

Please find the enclosed C code for i.mx6 NAND programming

Have a great day,
Yuri

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[dc101]

Is the BCC encode source code still available somewhere? Working with an iMX6 and iMX28.

[astreit]

Dear Yuri,

can you please provide me the source code for the bch_deco.c aswell? I need that for an analysis tool for NAND flash issues. @Grant Whitacre: Can you support us here?

Thanks a lot for your help!

Best regards,

Alex Streit

Freescale Supplier Manager @ Continental AG (BU I IC RD SP IP SSW)

[Yuri]

  Alexander, hello !

  I do not have (and - alas - cannot find) decoder sources :-( 

Regards,

Yuri.

[simonlie]

Thanks for the fast reply. I tried these generator polynomials before and it didn't work. I encoded data with my software and these generator polynomials and compared it with the checksum that was calculated from the hardware ECC unit for the exact same data, it didn't match.

The hardware must use some other generator polynomials.

Regards,

Simon

[Rodrigue]

Hi Simon,

the NAND driver of the ROM configures the BCH thanks to the information found in the FCB.

From the ref manual:

As part of the NAND media initialization, the ROM driver uses safe NAND timings to

search for a Firmware Configuration Block (FCB) that contains the optimum NAND

timings, page address of Discovered Bad Block Table (DBBT) Search Area and start

page address of primary and secondary firmware.

The hardware ECC level to use is embedded inside FCB block. The FCB data structure is

protected using software ECC (SEC-DED Hamming Codes). Driver reads raw 2112 bytes

of first sector and runs through software ECC engine that determines whether FCB data is

valid or not.

So you inform the NAND driver by configuring the FCB, see table 8-2

Best regards,

Rodrigue

[simonlie]

Hi Rodrigue,

thanks for the reply. It goes in the right direction :smileyhappy:. All what you say agrees with my state of knowledge, thats good! My problem goes a step further. For example I configure the FCB so, that the NAND driver has to use BCH8. Which generator polynomial is used by the hardware ECC unit to compute the checksum, for example BCH8 (I need BCH2 - 40)? I'm pretty sure there is no information in the ref manual about that.

Best regards,

Simon

[Rodrigue]

Actually, the information block size is fixed. it is 512Bytes. The configuration of the ECC is basically configuring the correction level for the 512B.

The total code block size also includes the parity bytes.

So we must therefore work in a Galois Field with > 4096Bits (to include ECC bits). Therefore GF(13). As in the RM example. See 17.2.3.

Then EccB0 (or N) are the parity bytes, the sum of all of them for a page should not exceed the number of available parity bytes forseen by the memory layout itself. If you need a correction level of 8, you need to enter EccBN = 8 in the FCB parameter (0x08). But you must make sure that you have enough parity bytes available.

At the End the number of parity bits are compute that way: GF x ECC i.e. in our case: 13 x 8 = 108Bits or 13 Bytes.

You just have to enter these parameter in the FCB.

[simonlie]

I'm afraid that we are talking past each other. My board is booting perfectly. But I need to know how the ECC engine is actually calculating the parity bits. Or more precisely I need to know the generator polynomial that is used by the ECC engine to calculate the parity bits.

Best regards,

Simon

[Rodrigue]

Ok Simon.

So indeed ther are several possible prime polynomials to generate the GF13 (BCH20) and GF14 (BCH40)

See below the polynomials being used:

//GF(13) = 0x201b

//GF(14) = 0x402b

In fact you need that if you are planning to use a gang programmer or JTAG to program the NAND Flash.

[simonlie]

Thank you very much! This will help, I hope :smileywink:. Do you have any tips how to calculate the generator polynomial out of that informations? I never did this before.

Thank you.

Simon

[Rodrigue]

I understand it that way:

GF(13) generator polynomial is: x^9+1

GF(14) generator polynomial is: x^10 + x

this polynomial are the one used to generate both GF, namely all the symbols of the field.

Then the parity generation polynomial based on the above primitive polynomial, for ECC 8.

"10010000011000100001111110110100101010101100011000100101101101111010111001101100010001110100100001101011010010011"