Multibin implementation on SD/MMC for i.MX53 with WEC7

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Multibin implementation on SD/MMC for i.MX53 with WEC7

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seetha
Contributor III

Hi all,

I want to implement multibin on SD/MMC for i.MX53 WEC7. I gone through the web page at the following address

FileNotFound*KA8OBpldIOVyJF4TQizdrAdM-RkQmOiWOHPkC3QliPneRKbGAwgwtZz3QV0inJ3TFRPiwVksHuttxNTfwA6HqNq/README.txt

But this post is for i.MX50/i.MX51 on WinCE6.0. There are some changes in the files that they have mentioned in the patch. And few files are newly added as well. I am confused with this.

Does anybody have implemented this multibin on SD/MMC on i.MX53 WEC7?

Please share the experience of implementing multibin on i.MX53.

Thanks in advance,

Seetharam

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KeshavaGN
Contributor V

Anybody have idea on this?? Qiang_FSL YuLin724 yucheng Yuri AdeneoEmbedded yusun ...  anybody please?

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qiang_li-mpu_se
NXP Employee
NXP Employee

There is also iMX53 WinCE700 patch: https://community.freescale.com/thread/280663


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KeshavaGN
Contributor V

Hi Qiang_FSL ,

Thanks for reply..

But I am confusing about using cfimager for flashing.

If I flash using cfimager and try to load the image, it is creating new MBR etc and will format the SD card. So image will be erased.

Solution for this ??

(EDIT: Code-wise, I have already implemented all the changes in that link)

Regards,

Keshava

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qiang_li-mpu_se
NXP Employee
NXP Employee

Hi Keshava,

cfimager -f eboot.nb0 -d F -raw -offset 0x400

The parameter "-raw" for cfimager will only write data to target address (-offset), no MBR create or sd card format.

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KeshavaGN
Contributor V

Thanks Qiang_FSL ,

Understood.

But before loading SD image, eboot is doing the following operations:

SDHCVerifyMultiBINMBR

SDHCCreateMultiBINMBR

(Prints on log:

Successfully created 3 partitions

Boot Partition size = 767 Kbytes, startSect = 0x2, totSect = 0x5fe.

BINFS Partition size = 32768 Kbytes, startSect = 0x600, totSect = 0x10000

File System Partition size = 3838720 Kbytes, startSect = 0x10600, totSect = 0x752600

INFO: Copying NK image to RAM address 0xa0200000

)

I'm suspecting this.

Is this OK? Or whether this will format the xip.nb0 that I have flashed??

Regards,

Keshava

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qiang_li-mpu_se
NXP Employee
NXP Employee

Hi Keshave, the EBoot will check and create the BINFS MBR for first time boot up. If the eboot.nb0 and xip.nb0 are built from the same project, no data will be destroyed.

So you just need write the EBOOT.nb0 and XIP.nb0 to sd card target address with cfimage.exe or the MFGTool, then EBOOT will do the remained work for BINFS support.

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KeshavaGN
Contributor V

Okay Qiang_FSL ,

I have implemented all the changes and built the image.

Flashed using below commands (refering to mfgtool source code)

cfimager -f eboot.nb0 -d F -raw -offset 0x400

cfimager -f eboot.nb0 -d F -raw -offset 0x80400

cfimager -f xip.nb0 -d F -raw -offset 0x120400

Eboot is booting properly.

But its not loading the OS image.

Below is the log.

INFO: Storing boot configuration to SDHC

INFO: Successfully stored boot configuration to SDHC

System ready!

Preparing for download...

Press [ENTER] to launch image stored in SD/MMC or [SPACE] to cancel.

Initiating image launch in 1 seconds.

0 seconds.

Launching flash image  ...

-BLMenu .

INFO: Using device name: 'MX6Q65535'

                                    INFO: Reading NK image to SDHC (please wait)...

SDImageCfg.dwNkRAMOffset = 10200000

pSectorBuf = a0200000

INFO: Inside If of BSP_SUPPORT_MULTIBIN...

Inside SDHCVerifyMultiBINMBR

SDHCVerifyMultiBINMBR -

SDHCVerifyMultiBINMBR - false

Card Capacity 3872256 (Kbytes)

SDHCCreateMultiBINMBR +

SDHCCreateMultiBINMBR memset

SDMMC_WriteSector>>

Successfully created 3 partitions

Boot Partition size = 767 Kbytes, startSect = 0x2, totSect = 0x5fe.

BINFS Partition size = 32768 Kbytes, startSect = 0x600, totSect = 0x10000

File System Partition size = 3838720 Kbytes, startSect = 0x10600, totSect = 0x752600

INFO: Copying NK image to RAM address 0xa0200000

numSectors = 512

INFO: Read is 100% complete

INFO: Copy of NK completed successfully

Either card is not eSD2.1, or boot partition is not created yet

Download successful!  Jumping to image at 0x0 (physical 0x10200000)...

There it stops :smileysad:

What may be the issue? Which part of the code I can suspect?

Thanks & regards,

Keshava

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qiang_li-mpu_se
NXP Employee
NXP Employee

Can you attach your ce.bib here?

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KeshavaGN
Contributor V

Sure , Qiang_FSL .

Attached.

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qiang_li-mpu_se
NXP Employee
NXP Employee

Hi Keshava, your config.bib should be wrong, from your ce.bib, it show chain.bin was put at address 80200000 ~ 80201000, the memory address 80200000 should be the kernel code running address.

Another issue in your ce.bib, there are no files in XIPKERNEL region and there are also no binfs sdmmc drivers.

So I think you havne't merged the BINFS patch correctly.

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KeshavaGN
Contributor V

Hi Qiang_FSL ,

I will check this and update.

Thanks for support

Regards,

Keshava

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KeshavaGN
Contributor V

Hi Qiang_FSL , I checked the config.bib of reference in link How to support MultiBIN(BINFS) on SDMMC for Freescale IMX5x WinCE 6.0/7.0 BSP -blog archive and merged the changes.

Still the issue is not solved. I have attached the updated ce.bib. Can you please help me on this ?

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qiang_li-mpu_se
NXP Employee
NXP Employee

The CONFIG and MEMORY section in ce.bib seems OK now. But the build script "MakeBinfsBib.js" hasn't been run on your BSP.

Please check the file name "WINCE700\PLATFORM\iMX53_SMD\FILES\imx53_SMD-preri.proj", if your BSP name is "iMX6Q_SABREAuto", this file should be renamed to "iMX6Q_SABREAuto-preri.proj".

Another thing needs be checked, you should make sure javascript can run on your PC. To check this, you can double click the "MakeBinfsBib.js" on your PC, the information should be like JS.jpg.

By the way, I still haven't seen any files be put into XIPKERNEL region, please double check your platform.bib.

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KeshavaGN
Contributor V

Thank you Qiang_FSL ..

I will check this...

Regards,

Keshava

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qiang_li-mpu_se
NXP Employee
NXP Employee

@

Hi Keshava, you'd better comapre my iMX53 SMD patch with original BSP and understand the modifications.

Your ce.bib is still far away to the multibin image.

The attached is a correct multibin ce.bib, you can find XIPKERNEL files like followed, and the binfs related SD card drivers must be in XIPKERNEL region:

    nk.exe          I:\PB6_WorkSpaces\iMX51-EVK-Mobility\RelDir\Freescale_i_MX51_EVK_ARMV4I_Release\oal.exe                  XIPKERNEL   MODULE   SHZ

...

; ESDHC Driver

;

    binfs_esdhc.dll       I:\PB6_WorkSpaces\iMX51-EVK-Mobility\RelDir\Freescale_i_MX51_EVK_ARMV4I_Release\binfs_esdhc.dll                    XIPKERNEL  SHK

    binfs_sdbus.dll       I:\PB6_WorkSpaces\iMX51-EVK-Mobility\RelDir\Freescale_i_MX51_EVK_ARMV4I_Release\binfs_sdbus.dll                    XIPKERNEL  SHK

    binfs_sdmemory.dll       I:\PB6_WorkSpaces\iMX51-EVK-Mobility\RelDir\Freescale_i_MX51_EVK_ARMV4I_Release\binfs_sdmemory.dll                    XIPKERNEL  SHK

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KeshavaGN
Contributor V

Hi Qiang_FSL ,

Thank you.. Now I'm able to get the OS image (xip.nb0) loading...

But it's crashing (data abort exception) just after the OAL, and not proceeding.

Below is the log. Any idea on this?? (I have not modified the SD driver for the multibinfs implementation still. But I don't think this is the cause of this problem.. Please advice.)

LOG:

INFO: Copy of NK completed successfully

Either card is not eSD2.1, or boot partition is not created yet

Download successful!  Jumping to image at 0x0 (physical 0x10200000)...

INFO:OALLogSetZones: dpCurSettings.ulZoneMask: 0xb

BSP Clock Configuration:

    OSC            =  24000000 Hz

    PLL1 (CPU)      =  792000000 Hz

    PLL2 (BUS)      =  528000000 Hz

    PLL3 (USBOTG)  =  480000000 Hz

    PLL4 (AUDIO)    =          0 Hz

    PLL5 (VIDEO)    =          0 Hz

    PLL6 (MLB)      =          0 Hz

    PLL7 (USBHOST)  =  480000000 Hz

    PLL8 (ENET)    =          0 Hz

    PLL1_REF        =  24000000 Hz

    PLL2_BURNIN    =          0 Hz

    PLL3_60M        =  60000000 Hz

    PLL3_80M        =  80000000 Hz

    PLL3_120M      =  120000000 Hz

    480M_PFD0_720M  =  720000000 Hz

    480M_PFD1_540M  =          0 Hz

    480M_PFD2_508M  =  508235294 Hz

    480M_PFD3_454M  =  454736842 Hz

    528M_PFD0_352M  =  352000000 Hz

    528M_PFD1_594M  =  594000000 Hz

    528M_PFD2_400M  =  396000000 Hz

    528M_PFD3_200M  =  594000000 Hz

    ARM            =  792000000 Hz

    AXI            =  264000000 Hz

    PERIPH          =  528000000 Hz

    MMDC_CH0_AXI    =  528000000 Hz

    MMDC_CH1_AXI    =  528000000 Hz

    AHB_132M        =  132000000 Hz

    IPG            =  66000000 Hz

    PERCLK          =  66000000 Hz

    CKIL_SYNC      =          0 Hz

    CKIH            =          0 Hz

    IPU2_HSP        =  264000000 Hz

    IPU1_HSP        =  264000000 Hz

    PCIE_AXI        =  264000000 Hz

    VDO_AXI        =  264000000 Hz

    VPU_AXI        =  264000000 Hz

    USDHC1          =  198000000 Hz

    USDHC2          =  198000000 Hz

    USDHC3          =  198000000 Hz

    USDHC4          =  198000000 Hz

    SSI1            =  63529411 Hz

    SSI2            =  63529411 Hz

    SSI3            =  63529411 Hz

    CAN            =  30000000 Hz

    UART            =  80000000 Hz

    SPDIF0          =  30000000 Hz

    SPDIF1          =  30000000 Hz

    ESAI            =  30000000 Hz

    ECSPI          =  60000000 Hz

    ACLK_EMI_SLOW  =  132000000 Hz

    ACLK_EMI        =  132000000 Hz

    ENFC            =  24000000 Hz

    HSI_TX          =  198000000 Hz

    VIDEO_27M      =          0 Hz

    LDB_DI0_SERIAL  =          0 Hz

    LDB_DI1_SERIAL  =          0 Hz

    LDB_DI0_IPU    =          0 Hz

    LDB_DI1_IPU    =          0 Hz

    IPU1_DI0        =          0 Hz

    IPU1_DI1        =          0 Hz

    IPU2_DI0        =          0 Hz

    IPU2_DI1        =          0 Hz

    ASRC            =          0 Hz

    WRCK            =          0 Hz

    GPU2D_CORE      =  352000000 Hz

    GPU2D_AXI      =  264000000 Hz

    GPU3D_CORE      =  528000000 Hz

    GPU3D_AXI      =  264000000 Hz

    GPU3D_SHADER    =  594000000 Hz

    IPP_DI0        =          0 Hz

    IPP_DI1        =          0 Hz

Windows CE Kernel for ARM (Thumb Enabled)

PL310 ID = 0x410000c7

L2 cache enabled

OEMInit:  silicon rev = 0x13

BoardID = 0xffff.

pdwXIPLoc = 0x70200000

WARN: OALKitlInit: KITL Disabled

SMP support disabled

dwFshFnRsvd = 0x0

cbNKPagingPoolSize = 0x200000

pdwCurXIP = 0x80200000

dwNumXIPs = 0xea0003fe

Number of XIPs exceeds MAX

All xip's added

-OEMInit

PID:00400002 TID:00510002 OALIoCtlHalInitRTC(2006/1/1 12:0:0.000)

PID:00400002 TID:00510002 WARNING: SNVS was reset.

PID:00400002 TID:00510002 Exception 'Data Abort' (0x4): Thread-Id=00510002(pth=c080262c), Proc-Id=00400002(pprc=8065f5e0) 'NK.EXE', VM-active=00400002(pprc=8065f5e0) 'NK.EXE'

PID:00400002 TID:00510002 PC=effb29d8(k.coredll.dll+0x000629d8) RA=eff8e96c(k.coredll.dll+0x0003e96c) SP=c48df6b0, BVA=00000000

PID:00400002 TID:00510002 Exception 'Data Abort' (0x4): Thread-Id=00510002(pth=c080262c), Proc-Id=00400002(pprc=8065f5e0) 'NK.EXE', VM-active=00400002(pprc=8065f5e0) 'NK.EXE'

PID:00400002 TID:00510002 PC=effb29d8(k.coredll.dll+0x000629d8) RA=eff8e96c(k.coredll.dll+0x0003e96c) SP=c48dfb88, BVA=00000000

Attached the ce.bib too.

Thanks.

With regards,

Keshava

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qiang_li-mpu_se
NXP Employee
NXP Employee

Hi Keshava, you had defined pdwXIPLoc to wrong address 0x70200000 in your config.bib, that is not needed, please remove it.

  nk.exe:pdwXIPLoc    00000000          70200000          FIXUPVAR

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KeshavaGN
Contributor V

Hi Qiang_FSL ,

Thank you for confirming this... (I added it just to test, as I saw this in one other ref BSP.)

I tested by removing this. Attached the new ce.bib.

Below is the log.

Windows CE Kernel for ARM (Thumb Enabled)

PL310 ID = 0x410000c7

L2 cache enabled

OEMInit:  silicon rev = 0x13

BoardID = 0xffff.

pdwXIPLoc = 0xffffffff

WARN: OALKitlInit: KITL Disabled

SMP support disabled

dwFshFnRsvd = 0x0

cbNKPagingPoolSize = 0x0

No proper XIP return

All xip's added

-OEMInit

PID:00400002 TID:00510002 OALIoCtlHalInitRTC(2006/1/1 12:0:0.000)

PID:00400002 TID:00510002 WARNING: SNVS was reset.

PID:00400002 TID:00510002 Exception 'Data Abort' (0x4): Thread-Id=00510002(pth=c080262c), Proc-Id=00400002(pprc=8065f5e0) 'NK.EXE', VM-active=00400002(pprc=8065f5e0) 'NK.EXE'

PID:00400002 TID:00510002 PC=effb29d8(k.coredll.dll+0x000629d8) RA=eff8e96c(k.coredll.dll+0x0003e96c) SP=c48df6b0, BVA=00000000

PID:00400002 TID:00510002 Exception 'Data Abort' (0x4): Thread-Id=00510002(pth=c080262c), Proc-Id=00400002(pprc=8065f5e0) 'NK.EXE', VM-active=00400002(pprc=8065f5e0) 'NK.EXE'

PID:00400002 TID:00510002 PC=effb29d8(k.coredll.dll+0x000629d8) RA=eff8e96c(k.coredll.dll+0x0003e96c) SP=c48dfb88, BVA=00000000

Thanks

Regards,

Keshava

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qiang_li-mpu_se
NXP Employee
NXP Employee

All pdwXIPLoc related codes are not needed.

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KeshavaGN
Contributor V

Yes Qiang_FSL , Even I thought of same...

I removed this extra code in OALInit. But it is not solving the issue. Below is the log.

I will try merging the only missing implementation, i.e. SD card driver changes.

But I don't think it is causing this crash, as SD driver is not loaded still...

New log:

Windows CE Kernel for ARM (Thumb Enabled)

PL310 ID = 0x410000c7

L2 cache enabled

OEMInit:  silicon rev = 0x13

BoardID = 0xffff.

WARN: OALKitlInit: KITL Disabled

SMP support disabled

-OEMInit

PID:00400002 TID:00510002 OALIoCtlHalInitRTC(2006/1/1 12:0:0.000)

PID:00400002 TID:00510002 Exception 'Data Abort' (0x4): Thread-Id=00510002(pth=c080262c), Proc-Id=00400002(pprc=8065f5e0) 'NK.EXE', VM-active=00400002(pprc=8065f5e0) 'NK.EXE'

PID:00400002 TID:00510002 PC=effb29d8(k.coredll.dll+0x000629d8) RA=eff8e96c(k.coredll.dll+0x0003e96c) SP=c48df6b0, BVA=00000000

PID:00400002 TID:00510002 Exception 'Data Abort' (0x4): Thread-Id=00510002(pth=c080262c), Proc-Id=00400002(pprc=8065f5e0) 'NK.EXE', VM-active=00400002(pprc=8065f5e0) 'NK.EXE'

PID:00400002 TID:00510002 PC=effb29d8(k.coredll.dll+0x000629d8) RA=eff8e96c(k.coredll.dll+0x0003e96c) SP=c48dfb88, BVA=00000000

Thanks

Regards,

Keshava

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