Hello,
Please look at the example (in attachments) of the following thread how to run multiple cores.
Integrating Processor Expert for i.MX and ARM GCC with Eclipse
Below are some comments :
"Upon initial power-up of the iMX6QD, each of the Cortex-A9 cpu’s will attempt to by default start executing at the ARM reset exception vector (at address: 0x00000000) after they are released from reset. This space in memory in the iMX6QD memory map is part of the on-chip boot ROM. The boot ROM code uses the state of the eFuses and/or boot GPIO settings to determine the boot behavior of the device using CPU0 (where CPU0 - CPU3 can be available on the chip depending on which version, iMX6Quad or iMX6Dual is being used). This is boot process is described in detail in the “System Boot” chapter of the reference manual.
Activating the Other cpu’s
Even though there are multiple cores available, only CPU0 is automatically activated during the initial boot/power-up process. Upon initial boot/power-up, the other available secondary cores are left in a reset state. The reset signal for each of the cores is handled by the “System Reset Controller” module, and after power-up the SRC module keeps the secondary cores in a reset state. Therefore, it is up to the application to enable the other available cores; this is not part of the boot ROM.
The other available cores can be enabled by setting the core#_enable signal for each of the cores in the SRC Control Register (bits 22:24, for core1, core2, and core3 respectively). Once the enable bits are set, that corresponding core will get released from its reset state and it will then start to execute the boot ROM (at: 0x0000000).
High-Level Boot ROM Overview
Initially, the boot ROM needs to distinguish which CPU is currently booting up, so it will check the CPU ID (this stored in the CotexA9 Multiprocessor Affinity register, see the CortexA9 technical reference manual for more details).
If CPU0 is booting up, then the boot ROM will first go through its boot process described in the System Boot chapter of the reference manual. There it determines where to boot the image from, and after going through all the HAB checks, the image is loaded and executed.
If the CPU booting is not CPU0, then the boot ROM will check what is referred to as “Persistent Bits” in the reference manual to determine if that CPU has a valid pointer it can execute from. The “persistent bits” are a collection of registers that are used by the boot ROM code where it expects valid pointers to executable regions/functions for each core. The registers that the boot ROM uses are some of the General Purpose Registers in the SRC module. These registers are used because since by design, the SRC GPR registers retain their values even after a warm reset. They are listed in the table below. For full details on boot process and the “persistent bits”, refer to the iMX6QD reference manual."
Have a great day,
Yuri
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