with this device tree :
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio =<&reset_ic 0 1>;
child-reset-gpios = <&reset_ic 3 1
&reset_ic 2 1
&reset_ic 1 1>;
#gpio-cells = <3>;
status = "okay";
fsl,max-link-speed = <2>;
/*
* PCI bridge: PLX Technology, Inc. PEX 8605 PCI Express
4-port Gen2 Switch
* Port 0 to CPU, Port 1 to igb and ports 2 and 3 are accessible through
* the half and full size mini PCIe slots on the board.
*/
pcie@1,0 {
/* Connection to CPU */
status = "okay";
fsl,max-link-speed = <2>;
};
pcie@2,1 {
/* Connection to Intel Gigabit Ethernet Controller*/
status = "okay";
fsl,max-link-speed = <1>;
pcie@3,0 {
/* The igb */
status = "okay";
fsl,max-link-speed = <1>;
eth0: igb0 {
compatible = "intel,igb";
/*pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;*/
phy-mode = "mii";
phy-handle = <ð0>;
phy-reset-gpios = <&reset_ic 4 GPIO_ACTIVE_LOW>;
phy-reset-duration = <100>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
switch: switch@0 {
compatible ="marvell,mv88e6085";
reg = <0>;
dsa,member = <0 0>;
eeprom-length = <512>;
interrupt-parent = <&gpio2>;
interrupts =<31IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <2>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "port0";
phy-handle = <&switchphy0>;
};
port@1 {
reg = <1>;
label = "port1";
phy-handle = <&switchphy1>;
};
port@2 {
reg = <2>;
label = "port0";
phy-handle = <&switchphy2>;
};
port@5 {
reg = <5>;
label = "cpu";
ethernet = <ð0>;
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
switchphy0:switchphy@0 {
reg = <0>;
interrupt-parent = <&switch>;
interrupts =<0 IRQ_TYPE_LEVEL_HIGH>;
};
switchphy1:switchphy@1 {
reg = <1>;
interrupt-parent = <&switch>;
interrupts =<1 IRQ_TYPE_LEVEL_HIGH>;
};
switchphy2:switchphy@2 {
reg = <2>;
interrupt-parent = <&switch>;
interrupts =<2 IRQ_TYPE_LEVEL_HIGH>;
};
};
};
};