MX7D ENET1 MII Receive

[dietersteininge]

We´re using UBoot v2016.03_4.1.15_2.0.0_ga with i.MX7D and a Micrel PHY KSZ8061MNG (10/100MBit, MII-Interface).

Transmitting Frames ist working (using the ping command, i can see the ARP request/response on Wireshark), but i didn´t receive any frame.

The PHY asserts the Receive Data Valid Signal, so it seems that the PHY gets the ARP response and sent it to the MX7.

here are my settings:

/* Network */
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_FEC_MXC
#define CONFIG_MII
#define CONFIG_FEC_XCV_TYPE             MII100
#define CONFIG_ETHPRIME                 "FEC"
#define CONFIG_PHYLIB
#define CONFIG_FEC_ENET_DEV 0

#if (CONFIG_FEC_ENET_DEV == 0)
#define IMX_FEC_BASE            ENET_IPS_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR          0x0
#elif (CONFIG_FEC_ENET_DEV == 1)
#define IMX_FEC_BASE            ENET2_IPS_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR          0x1
#endif

#define CONFIG_FEC_MXC_MDIO_BASE    ENET_IPS_BASE_ADDR

and my initialisations in board.c

#ifdef CONFIG_FEC_MXC
static iomux_v3_cfg_t const fec1_pads[] = {
    MX7D_PAD_ENET1_RX_CLK__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
    MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
    MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
    MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
    MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
    MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
    MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),

    MX7D_PAD_ENET1_TX_CLK__ENET1_TX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
    MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
    MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
    MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
    MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
    MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
    MX7D_PAD_ENET1_RGMII_TXC__ENET1_TX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),

    MX7D_PAD_ENET1_CRS__ENET1_CRS | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
    MX7D_PAD_ENET1_COL__ENET1_COL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),

    MX7D_PAD_GPIO1_IO10__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
    MX7D_PAD_GPIO1_IO11__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
};

static iomux_v3_cfg_t const fec2_pads[] = {
    MX7D_PAD_EPDC_BDR1__ENET2_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
    MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
    MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
    MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
    MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
    MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
    MX7D_PAD_EPDC_SDCE1__ENET2_RX_ER | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),

    MX7D_PAD_EPDC_BDR0__ENET2_TX_CLK  | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
    MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0  | MUX_PAD_CTRL(ENET_PAD_CTRL),
    MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1  | MUX_PAD_CTRL(ENET_PAD_CTRL),
    MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2  | MUX_PAD_CTRL(ENET_PAD_CTRL),
    MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3  | MUX_PAD_CTRL(ENET_PAD_CTRL),
    MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL  | MUX_PAD_CTRL(ENET_PAD_CTRL),
    MX7D_PAD_EPDC_GDSP__ENET2_TX_ER  | MUX_PAD_CTRL(ENET_PAD_CTRL),

    MX7D_PAD_EPDC_PWR_COM__ENET2_CRS | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
    MX7D_PAD_EPDC_PWR_STAT__ENET2_COL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),

    MX7D_PAD_GPIO1_IO14__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
    MX7D_PAD_GPIO1_IO15__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
};

static void setup_iomux_fec(void)
{
    if (0 == CONFIG_FEC_ENET_DEV) {
        imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
    } else {
        imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads));
    }
}

int board_eth_init(bd_t *bis)
{
    int ret;

    setup_iomux_fec();

    ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
        CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
    if (ret)
        printf("FEC1 MXC: %s:failed\n", __func__);

    return ret;
}

static int setup_fec(int fec_id)
{
    struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
        = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;

    if (0 == fec_id) {
        /* clk from phy, clear gpr1[17], set gpr1[13] */
        clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
                IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK,
                IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK);

        printf("reset FEC0 phy\n");
        gpio_direction_output(IMX_GPIO_NR(6, 9) , 0);
        udelay(500);
        gpio_direction_output(IMX_GPIO_NR(6, 9) , 1);

    } else {
        /* clk from phy, clear gpr1[18], set gpr1[14] */
        clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
                IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_MASK,
                IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_MASK);

    }

    return set_clk_enet(ENET_25MHz);
}

int board_phy_config(struct phy_device *phydev)
{
    if (phydev->drv->config)
        phydev->drv->config(phydev);

    return 0;
}
#endif

Any ideas, why receiving frames doesn't work?

---

The picture "ethernet.jpg" shows the connections between MX7D and the PHY.

And here are some Ethernet registers from the MX7D after three transmitted ping-frames.

ecntrl       0x70000102
mib_control  0x40000000
r_cntrl      0x5ee0024
paddr1       0x190500
paddr2       0x18808
racc         0x0

rmon_t_packets    3
rmon_t_bc_pkt     3
rmon_t_mc_pkt     0

rmon_r_packets    0
rmon_r_bc_pkt     0
rmon_r_mc_pkt     0
rmon_r_crc_align  0
rmon_r_undersize  0
rmon_r_oversize   0
rmon_r_frag       0
rmon_r_jab        0
rmon_r_octets     0
ieee_r_drop   0
ieee_r_frame_ok 0
ieee_r_crc    0
ieee_r_align  0
rmon_r_macerr     0
rmon_r_fdxfc      0
ieee_r_octtets_ok 0

[dietersteininge · Accepted solution]

Got it,

ENET1_RX_CLK_SELECT_INPUT DAISY Register was set to ENET1_RGMII_RXC_ALT0 instead of ENET1_RX_CLK_ALT0.

[gusarambula]

Hello Dieter Steininger,

Thank you for posting the solution to this! I'm sure it will help other Community users!

Regards,