MX6q - Different between Analog ARM PLL control Register

[anson]

Hi,

I'm using imx6q processor. Found that the following registers are identical in structure, but what is the different?

CCM_ANALOG_PLL_ARM  (Addr: 0x020C8000)

CCM_ANALOG_PLL_ARM_SET (Addr: 0x020C8004)

CCM_ANALOG_PLL_ARM_CLR (Addr: 0x020C8008)

CCM_ANALOG_PLL_ARM_TOG (Addr: 0x020C800C)

[Yuri · Accepted solution]

Three registers (set, clr, tog) approach is used to optimize bit manipulation.

In order to avoid read – modify – write cycles as separate (non-atomic)

operations (which may be occasionally interrupted), three registers for bit setting,

bit clearing and bit toggle are implemented :

  CCM_ANALOG_PLL_ARM  register has corresponding SET, CLR and TOG registers,

which provide atomic bit manipulations. As the name of the register implies, a value

written to a SET, CLR or TOG register effectively performs the implied operation, but only

bits specified as ‘1’ are modified. Bits specified as ‘0’ are not modified.

Have a great day,
Yuri

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[AnsonHuang]

Hi, Anson

     The register offset of 0x0 is the basic register, you can read or write it. The offset of 0x4 is a set register, which means when you want to set some bits, you don't have to read it out, set the value and then write it into the register, for example, if you want to set bit 0~3 of this PLL register, you can just write 0x7 to 0x20c8004, if you use 0x20c8000 to do same thing, you have to read its value out, then do an "orr" with 0x7, then write it to 0x20c8000. The offset of 0x8 is a clear register, for example, writing a 0x7 to this register will clear bit 0~3. The offset of 0xc is a toggle register, writing 0x1 to this register will make bit 0 toggle.