Our BSP and demo codes only sets by-pass settings for CSI1 for some reason, here is what we usually have:
- reg32setbit(MIPI_HSC_BASE_ADDR+0x800,16);
- reg32setbit(MIPI_HSC_BASE_ADDR+HSC_MCD_OFFSET,10);
Now we need the following register settings to by-pass both CSI1 and CSI2
reg32_write(MIPI_HSC_BASE_ADDR+HSC_MCD_OFFSET, 0x00000F00); // @ECA
reg32_write(MIPI_HSC_BASE_ADDR+MCG_MCCMC_OFFSET, 0x0000000C); // @ECA
reg32_write(MIPI_HSC_BASE_ADDR+MXT_CONF_OFFSET, 0xF003008B); // @ECA