I am using the i.MX 6SoloX board with a Linux image in the Cortex-A9 and FreeRTOS in Cortex-M4. I am trying to use the OCRAM as shared memory between both cores.
If we look to the memory maps tables, it can be seen that the A9 is 0x90000-0x91FFFF and M4 is 20900000-2091FFFF.
In Linux dtb I have set the following shared memory:
fsl,shared-mem-addr = <0x91F000>;
fsl,shared-mem-size = <0x1000>;
Therefore, in FreeRTOS I want to read the following memory range and I set the permission in the RDC. (hardware_init.c)
uint32_t start, end;
start = 0x20910000;
end = 0x2091FFFF;
RDC_SetMrAccess(RDC, rdcMrOcram, start, end, 0xFF, true, false);
If a I write something in the RAM memory, the only way I have get to read it through the Cortex-M4 is disabling the Cache memory in system_MCIMX6X_M4.c.
LMEM_PSCCR = (LMEM_PSCCR_ENWRBUF_MASK /*| LMEM_PSCCR_ENCACHE_MASK*/);
However, I only want to disable it for the OCRAM, not for the whole system. I tried with the MPU but I do not get the desired result. I program it in region 1 with the following features (TEX 000 / C 1 / B 0 / S 1 / AP 011 / 64KB).
Why I do not get to read the data if I disable the cache for it? Do I disable it correctly?
/* M4 core clock root configuration. */
/* Initialize MPU */
/* Make sure outstanding transfers are done. */
__DMB();
/* Disable the MPU. */
MPU->CTRL = 0;
/* Select Region 0 to configure DDR memory(1MB). */
MPU->RNR = 0;
MPU->RBAR = 0x80000000;
MPU->RASR = 0x030B0027;
/* Select Region 1 to configure share memory with A9(1M). */
MPU->RNR = 1;
MPU->RBAR = 0x20910000;
MPU->RASR = 0x306001F;
/* Select Region 2 to configure ocram. */
MPU->RNR = 2;
MPU->RBAR = 0;
MPU->RASR = 0;
/* Select Region 3 to configure QSPI memory. */
MPU->RNR = 3;
MPU->RBAR = 0x60000000;
MPU->RASR = 0x030B0029;
/* Disable unused regions. */
MPU->RNR = 4;
MPU->RBAR = 0;
MPU->RASR = 0;
MPU->RNR = 5;
MPU->RBAR = 0;
MPU->RASR = 0;
MPU->RNR = 6;
MPU->RBAR = 0;
MPU->RASR = 0;
MPU->RNR = 7;
MPU->RBAR = 0;
MPU->RASR = 0;
/* Enable Privileged default memory map and the MPU. */
MPU->CTRL = MPU_CTRL_ENABLE_Msk |
MPU_CTRL_PRIVDEFENA_Msk;
/* Memory barriers to ensure subsequence data & instruction
* transfers using updated MPU settings.
*/
__DSB();
__ISB()
