MMC wp default setting is always high in imx6ul

[anantharamachan]

Hi,

This is in continuation with conversation we had in mmc wp - imx6ul 

I made changes as below in DTS for imx6ul:

&usdhc1 {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_usdhc1>;
    cd-gpios = <&gpio2 21 0>;
    wp-gpios = <&gpio4 25 1>;
    wp-inverted;
    no-1-8-v;
    keep-power-in-suspend;
    enable-sdio-wakeup;
    status = "okay";
};

        pinctrl_usdhc1: usdhc1grp {
            fsl,pins = <
                MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x17059  
                MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x17059
                MX6UL_PAD_CSI_DATA04__GPIO4_IO25   0x17059 //wp pin
                MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
                MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
                MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
                MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
            >;
        };

but the SD card gets write protected right from bootup, so boot up is failing always.

console output:

Starting kernel ...

[    0.001400] clocksource_of_init: no matching clocksources found
[    0.004518] /cpus/cpu@0 missing clock-frequency property
[    1.781728] cpu cpu0: dev_pm_opp_get_opp_count: device OPP not found (-19)
[    2.366058] EXT4-fs (mmcblk0p3): write access unavailable, cannot proceed
[    2.379833] Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(179,3)

I need an option to set default direction of this pin "MX6UL_PAD_CSI_DATA04__GPIO4_IO25 " to input & set it to low by default so that the board boots up normally. while board is functioning, the pin will be set to make the SD card write protected. 

Am i missing any details in DTB? kindly suggest.

BR,

Anantha R

[anantharamachan]

Hi Igor,

>>wp signal is optional, you can apply to emmc vendor support

I understand. but I assumed from spec & forums that the changes which we do is applicable only from processor side.

the emmc vendor [say,  sandisk], doesnt have any control on wp signalling.

when wp signal is enabled, the usdhc buffers will be cleared & further transmission of data through the lines will be stopped is what I understood. Please correct me if my understanding is wrong. 

we are working on this feature to block writes to SD card on power shutdown.

Can you kindly let me know if we need emmc vendor support to proceed on this?

BR,

Anantha R

[igorpadykov]

Hi Anantha

I think you can try to get additional help from emmc vendor support

and provide wp diagrams for each use case.

Best regards
igor

[anantharamachan]

Hi Igor,

Thanks for the input. I made below changes :

in u-boot:

#define USDHC_WP_PAD_CTRL (NO_PAD_CTL(1 << 31))

#define USDHC1_WP_GPIO (IMX_GPIO_NR(4, 25))

static iomux_v3_cfg_t usdhc1_wp_pads[] = {
        (MX6_PAD_CSI_DATA04__GPIO4_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};

imx_iomux_v3_setup_multiple_pads(usdhc1_wp_pads, ARRAY_SIZE(usdhc1_wp_pads));
gpio_direction_input(USDHC1_WP_GPIO);

ret = gpio_get_value(USDHC1_WP_GPIO);

has been added to pad changes to the wp pin.

in DTB:

&usdhc1 {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_usdhc1>;
    gpio-controller;
    #gpio-cells = <2>;
    cd-gpios = <&gpio2 21 0>;
    #gpio-cells = <2>;
    wp-gpios = <&gpio4 25 0>;
    input;    
    no-1-8-v;
    keep-power-in-suspend;
    enable-sdio-wakeup;
    status = "okay";
};

        pinctrl_usdhc1: usdhc1grp {
            fsl,pins = <
                MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x17059  
                MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x17059
                MX6UL_PAD_CSI_DATA04__GPIO4_IO25   0x80000000
                MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
                MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
                MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
                MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
            >;
        };

But now the problem is, I'm able to see

1. The SD card is write protected either write protected from bootup [if the pin is set to high], or

2. not write protected from boot up [if the pin is low]. in such case, even after bootup, if the pin is changed to high, write protect is not getting applied. i'm still able to write to the SD card.

Am I missing something? or some changes still needed? or is it expected behaviour? can we apply write protection to uSDHC during run time? Kindly clarify. Thanks.

BR,

Anantha R

[igorpadykov]

Hi Anantha 

wp signal is optional, you can apply to emmc vendor support

to know how to use it with that specific emmc part.

Best regards
igor

[igorpadykov]

Hi Anantha

one can configure that pad for low by default in uboot and then use dts setting:

NO_PAD_CTL(1 << 31): indicate this pin does not need config.

fsl,imx-pinctrl.txt\pinctrl\bindings\devicetree\Documentation - linux-imx - i.MX Linux kernel 

If pin is set to input then it is necessary to add external pull resistor or configure

internal pull using IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04 register.

Best regards
igor
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