MIPI Camera Frame corruption in IMX8MM when MIPI_DOUBLE_CMPNT and MIPI_YU_SWAP is enabled in CSI_CSICR18

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MIPI Camera Frame corruption in IMX8MM when MIPI_DOUBLE_CMPNT and MIPI_YU_SWAP is enabled in CSI_CSICR18

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ashwanthselvam
Contributor III

MIPI Camera frame corruption occurs in IMX8MM when MIPI_DOUBLE_CMPNT and MIPI_YU_SWAP is enabled in CSI_CSICR18 (CSI Control Register 18).

The same works in IMX8M.

I know that the MIPI CSI drivers are different for IMX8M and IMX8MM. Is there something that has to be done in addition, in MIPI CSI driver of IMX8MM to mimic the same behaviour as IMX8M? gogoer

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haidong_zheng
NXP Employee
NXP Employee

Hi Ashwanth:

Any way I will sync this issue internally. 

Before get result please try below patch for you issue.  This patch is based on 4.14.98 GA 2.0 

diff --git a/drivers/media/platform/mxc/capture/mxc_mipi_csi.c b/drivers/media/platform/mxc/capture/mxc_mipi_csi.c
index a7964b7b8345..5b4fec5dd9b3 100644
--- a/drivers/media/platform/mxc/capture/mxc_mipi_csi.c
+++ b/drivers/media/platform/mxc/capture/mxc_mipi_csi.c
@@ -488,6 +488,8 @@ static void __mipi_csis_set_format(struct csi_state *state)
 val = (val & ~MIPI_CSIS_ISPCFG_FMT_MASK) | state->csis_fmt->fmt_reg;
 mipi_csis_write(state, MIPI_CSIS_ISPCONFIG_CH0, val);
+ pr_info("fmt: %#x, %d x %d; CONFIG:0x%x \n", mf->code, mf->width, mf->height, val);
+
 /* Pixel resolution */
 val = mf->width | (mf->height << 16);
 mipi_csis_write(state, MIPI_CSIS_ISPRESOL_CH0, val);
@@ -522,8 +524,11 @@ static void mipi_csis_set_params(struct csi_state *state)
 val |= MIPI_CSIS_ISPCFG_ALIGN_32BIT;
 else /* Normal output */
 val &= ~MIPI_CSIS_ISPCFG_ALIGN_32BIT;
+ val |= 1 << 12;
 mipi_csis_write(state, MIPI_CSIS_ISPCONFIG_CH0, val);
+ pr_info(" mipi_csis_set_params CONFIG:0x%x\n", val);
+
 val = (0 << MIPI_CSIS_ISPSYNC_HSYNC_LINTV_OFFSET) |
 (0 << MIPI_CSIS_ISPSYNC_VSYNC_SINTV_OFFSET) |
 (0 << MIPI_CSIS_ISPSYNC_VSYNC_EINTV_OFFSET);

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haidong_zheng
NXP Employee
NXP Employee

Hi Selvam:

I'm not sure soc validation team verified those bits, please specify your test environment.

pastedImage_1.png

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ashwanthselvam
Contributor III

I am testing with a 4 lane AR1335 MIPI Camera. The data format of the sensor is UYVY. Since the waylandsink of Gstreamer supports YUYV, I need to swap the bits to avoid using a videoconverter. Since using a videoconverter means a drop in framerate.  By enabling the MIPI_DOUBLE_CMPNT and MIPI_YU_SWAP, I was able to stream using wayland sink in IMX8M, but when I tried the same in IMX8MM, frame corruption happens.

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haidong_zheng
NXP Employee
NXP Employee

Hi Ashwanth:

Have you tried my patch ? what is the result ?

Best Regards .

Tom.

Tom.Zheng(郑海东)

System Engineering.

Microcontroller Group. NXP Semiconductors

Address: No 192, LiangJing Road, Pudong New District, Shanghai, China

Phone: 86 21 28937181

Postcode 201203

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ashwanthselvam
Contributor III

Hi,

On enabling MIPI_CSIS_ISPCFG_DOUBLE_CMPNT (1 << 12) as per your patch, base address switching Change Err occurs. (BIT_ADDR_CH_ERR_INT)

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haidong_zheng
NXP Employee
NXP Employee

MIPI_CSIS_ISPCFG_DOUBLE_CMPNT (1 << 12) ? 

My patch is not enable this bit. This patch set pixel mode as 01. 

pastedImage_1.png

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ashwanthselvam
Contributor III

Yes,

Setting Dual pixel mode causes base address switching error

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haidong_zheng
NXP Employee
NXP Employee

Understood. But internal team still suggest configure this field.

Best Regards .

Tom.

Tom.Zheng(郑海东)

System Engineering.

Microcontroller Group. NXP Semiconductors

Address: No 192, LiangJing Road, Pudong New District, Shanghai, China

Phone: 86 21 28937181

Postcode 201203

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ashwanthselvam
Contributor III

Setting Dual pixel mode causes base address switching error(BIT_ADDR_CH_ERR_INT). Is there any workaround for this?

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haidong_zheng
NXP Employee
NXP Employee

Hi Ashwanth:

So far we did not have good way to solve your issue, 

But designer has below suggestion:

1: confirm camera sensor output double component data:

2: confirm CR18 BIT20/BIT21 MIPI_YU_SWAP/MIPI_DOUBLE_CMPNT be set

3: confirm bit 12/13 of MIPI_CSI_ISP_CONFIG0 PIXEL_MODE is 1 

4: Try set /clear CR18 BIT4/BIT5 BASEADDR_SWITCH_EN & BASEADDR_SWITCH_SEL 

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ashwanthselvam
Contributor III

Hi,

Tried your suggestion but no luck. The issue still exists.

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1,872 Views
haidong_zheng
NXP Employee
NXP Employee

Hi Ashwanth:

Any way I will sync this issue internally. 

Before get result please try below patch for you issue.  This patch is based on 4.14.98 GA 2.0 

diff --git a/drivers/media/platform/mxc/capture/mxc_mipi_csi.c b/drivers/media/platform/mxc/capture/mxc_mipi_csi.c
index a7964b7b8345..5b4fec5dd9b3 100644
--- a/drivers/media/platform/mxc/capture/mxc_mipi_csi.c
+++ b/drivers/media/platform/mxc/capture/mxc_mipi_csi.c
@@ -488,6 +488,8 @@ static void __mipi_csis_set_format(struct csi_state *state)
 val = (val & ~MIPI_CSIS_ISPCFG_FMT_MASK) | state->csis_fmt->fmt_reg;
 mipi_csis_write(state, MIPI_CSIS_ISPCONFIG_CH0, val);
+ pr_info("fmt: %#x, %d x %d; CONFIG:0x%x \n", mf->code, mf->width, mf->height, val);
+
 /* Pixel resolution */
 val = mf->width | (mf->height << 16);
 mipi_csis_write(state, MIPI_CSIS_ISPRESOL_CH0, val);
@@ -522,8 +524,11 @@ static void mipi_csis_set_params(struct csi_state *state)
 val |= MIPI_CSIS_ISPCFG_ALIGN_32BIT;
 else /* Normal output */
 val &= ~MIPI_CSIS_ISPCFG_ALIGN_32BIT;
+ val |= 1 << 12;
 mipi_csis_write(state, MIPI_CSIS_ISPCONFIG_CH0, val);
+ pr_info(" mipi_csis_set_params CONFIG:0x%x\n", val);
+
 val = (0 << MIPI_CSIS_ISPSYNC_HSYNC_LINTV_OFFSET) |
 (0 << MIPI_CSIS_ISPSYNC_VSYNC_SINTV_OFFSET) |
 (0 << MIPI_CSIS_ISPSYNC_VSYNC_EINTV_OFFSET);
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