Hi there,
I have some questions regarding the set up of the CSI and IPU blocks. Especially how they are set up in the current Linux implementation (kernel 3.14).
I'm trying to receive a MIPI-CSI2 camera input which is transmitting YUV422 (UYVY mode, the only mode specified in CSI2 standard).
1. CSI2IPU
I can't find any initialisation of this block in the code? Yet as far as I can tell it should be set to UYVY mode and non gated clock mode (iMX6 RM says non gated mode for MIPI but doesn't go into any detail on that).
According to the RM this block is only used for MIPI. Why is the default config YUYV and gated mode and never changed by the Linux drivers (even if MIPI camera is used, such as ov5640_mipi)?
2. IPU SENS_CONF
This register seems to be incorrectly configured for MIPI CSI2 cameras if using the mxc_v4l2_capture module. There is no way the mxc_v4l2_capture can pass IPU_CSI_CLK_MODE_NONGATED_CLK to the ipu_csi_init_interface() function. The only MIPI camera I can find is the ov5650_mipi and when using this clk mode (i.e. PRTCL field of SENS_CONF) is set to 0 (gated clock mode).
What are correct settings for SENS_CONF register for MIPI cameras? Regarding clock mode, and clk, data h/vsync polarity? This must depend on what CSI2PU outputs but it is not well documented.
The issue I'm seeing with my custom MIPI camera is that the IPU seems to miss End Of Frame events. I need to transmit multiple frames for the IPU to store one to memory, and then usually I get a New Frame Before End Of Frame IRQ status. My camera is sending start of frame / end of frame correctly as far as I can tell. I have tried setting the non gated clock mode etc, but it doesn't help. I'm transmitting with a 400 MHz MIPI CSI2 DDR clock with 4 lanes. The IPU is clocked at 270 MHz.
Best regards,
Kristoffer
