Hi,
I am working on an embedded project that uses the MIMXRT1020. In the project, we have a sampling chain that uses the internal ADC at a speed of around 300kHz. The sampling chain looks like this : The PIT triggers the ADC_ETC that triggers the DMA when the conversion is complete. When the DMA has stored 256 samples, a software interrupt is triggered to allow the transfer of these buffer to a bigger buffer. When 10 DMA buffer has been received, the DMA interrupt calls a function. This function is executed every 8.5 ms ((256*10)/300k = 8.5 ms).
At each 500 ms, another task, the task 2, executes some calculation over some other big buffer. The computation takes around 20 ms to execute. Some FFT and buffer transfer are done during the computation. We realized that during the 20 ms of computation, the function, call by the DMA interrupt, is not called every 8.5 ms but at a higher time delay. We suspect that it could be a bus problem. With all the load and store done in the task 2 we think that all the RAM access of the task may delay some DMA transfer. When we stop the task 2, there is no delay in the function call.
We have read about the bus in the system and tried to reorganize the buffer location in the different system's RAM, but it did not change anything. Here what we understood :
1) The DMA is connected to the IP bus.
2) The OCRAM is connected to the AXI64 bus.
3) The ITCM and DTCM are connected to the TCM interface.
Could it be possible to place the DMA buffer in the OCRAM and the task's buffer in the DTCM or the ITCM so that, when the ARM core executes a load or store, it does not use the AXI64 bus? During this time, the IP bus and the AXI64 bus would be used by the DMA to write the sample in the OCRAM? Is there another memory configuration that could help use achieved what we want to do? Is there a way to give priority to the DMA transfers?
I cannot but the code in the forum, but I would be happy to share it under a NDA agreement.
Thank you
