Linux based Device driver for RGB Display

[SAVIOR]

Since over 3 years we have been successfully using a RGB display for our main-board based on NXP-i.Mx6UL processor with embedded Linux version HardKnott.

Now we are making a new main-board based on NXP-i.Mx9352 processor with embedded Linux version Mickledore. We want to retain the RGB display which is used in our older board.

Our project is stuck because display is not working with our new board based on i.Mx9352, although the backlight of the RGB is coming on, nothing is getting displayed.

We need the Linux based device driver for our 5 inch RGB parallel display is 5 inch TFT of Sinda : SDT05004CT-40, having TFT driver IC as OTA7001A/OTA9960A.

Attached herewith is the technical specification of the RGB display and also the section of the schematic of our new main-board for display.

[Zhiming_Liu]

Hi @SAVIOR 

We can't  provide the driver about this TFT driver IC. How do you drive this panel on i.MX6ULL? The porting steps should be similiar on i.MX93.

Best Regards

Zhiming

[SAVIOR]

As informed earlier, we are making our new main-board on i.Mx9352 based on Yocto Version:4.2 (Mickledore, Kernel Ver:6.1.55), while our existing main-board on i.Mx6UL is based on Yocto Version:3.3(Hardknott, Kernel Ver:5.10.72).

We are looking for section of code required for making the parallel RGB display work in i.Mx9352 based on Mickledore. We need help on code with equivalent values, as was available in i.Mx6UL.

To clarify our requirement, we are showing below the section of .DTS file which is being used to handle the display in i.Mx6UL:

&lcdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcdif_dat
&pinctrl_lcdif_ctrl>;
display = <&display0>;
status = "okay";
display0: display {
bits-per-pixel = <16>;
bus-width = <24>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <25344000>;
hactive = <800>;
vactive = <480>;
hfront-porch = <40>;
hback-porch = <88>;
hsync-len = <48>;
vback-porch = <32>;
vfront-porch = <13>;
vsync-len = <3>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
};
};
};
pinctrl_lcdif_dat: lcdifdatgrp {
fsl,pins = <
MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79
MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79
MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79
MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79
MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79
MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
>;
};
pinctrl_lcdif_ctrl: lcdifctrlgrp {
fsl,pins = <
MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
/* used for lcd reset */
MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79
>;
};

Below is the section of code for RGB display in the .DTS file available in the BSP of i.Mx9352 which is not working :
&lcdif {
status = "okay";
 assigned-clock-rates = <445333333>, <148444444>, <400000000>,
 <133333333>;
};

[Zhiming_Liu]

Hi @SAVIOR 

Please refer the content of /arm64/freescale/imx93-9x9-qsb-ontat-wvga-panel.dts, set correct display format  in parallel_disp_fmt.

The most important is about clocks, please refer below steps.

[SAVIOR]

Hi Zhiming Liu,

Thanks for your detailed response on the query we had raised. It has really helped us to move forward.

We have now been able to manage to get Parallel RGB Display work on i.MX93 Processors based main-board, however we are now facing following problems:

1. RGB Display is working only when a Mipi Display (Using Mipi to HDMI Convertor) is attached to the main-board. Display resolution and bit per pixel value is also not as per information provided in the DTB file. Rather, it is picking the values from the display attached on Mipi Interface
2. It stops giving video feed on Parallel RGB Display when there is no Mipi Display attached to the main-board, or the MIPI entry is disabled in DTB file.
3. /sys/class/graphics/fb0 getting populated only if Mipi Display is connected.

We now request to please guide us on how to remove dependency of Mipi and route the display output to Parallel RGB Display only. We are giving below our current configuration parameters.

Development Environment:

• Yocto Release : Nanbield 4.3 (Kernel : 6.6.3)
• Evaluation Board : imx93-11x11-evk

DTB Setting:

       PinMuxing

DTB Setting:

PinMuxing

pinctrl_lcdif: lcdifgrp {

fsl,pins = <

MX93_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA00 0x00000003

MX93_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA01 0x00000003

MX93_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA02 0x00000003

MX93_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA03 0x00000003

MX93_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA04 0x00000003

MX93_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA05 0x00000003

MX93_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA06 0x00000003

MX93_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA07 0x00000003

MX93_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA08 0x00000003

MX93_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA09 0x00000003

MX93_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x00000003

MX93_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x00000003

MX93_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x00000003

MX93_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x00000003

MX93_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x00000003

MX93_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x00000003

MX93_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x00000003

MX93_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x00000003

MX93_PAD_GPIO_IO22__MEDIAMIX_DISP_DATA18 0x00000003

MX93_PAD_GPIO_IO23__MEDIAMIX_DISP_DATA19 0x00000003

MX93_PAD_GPIO_IO24__MEDIAMIX_DISP_DATA20 0x00000003

MX93_PAD_GPIO_IO25__MEDIAMIX_DISP_DATA21 0x00000003

MX93_PAD_GPIO_IO26__MEDIAMIX_DISP_DATA22 0x00000003

MX93_PAD_GPIO_IO27__MEDIAMIX_DISP_DATA23 0x00000003

>;

};

pinctrl_lcdif_ctrl: lcdifctrlgrp {

fsl,pins = <

MX93_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x00000003

MX93_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x00000003

MX93_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x00000003

MX93_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC    0x00000003

/* used for lcd reset */

MX93_PAD_CCM_CLKO4__GPIO4_IO29  0x00000000

>;

};

Display Configuration

&lcdif {

pinctrl-names = "default";

pinctrl-0 = <&pinctrl_lcdif

  &pinctrl_lcdif_ctrl>;

display = <&display0>;

assigned-clock-rates = <537600000>, <134400000>, <400000000>, <133333333>;

status = "okay";

display0: display@0 {

bits-per-pixel = <16>;

bus-width = <24>;

display-timings {

native-mode = <&timing0>;

timing0: timing0 {

clock-frequency = <13824000>;

hactive = <800>;

vactive = <480>;

hfront-porch = <18>;

hback-porch = <40>;

hsync-len = <6>;

vback-porch = <20>;

vfront-porch = <8>;

vsync-len = <3>;

hsync-active = <0>;

vsync-active = <0>;

de-active = <1>;

pixelclk-active = <0>;

};

};

};

};

Disabling Pin Conflict

&flexcan2 {

status = "disabled";

 };

&xcvr {

        status = "disabled";

 };

&sai3 {

     status = "disabled";

};

[Zhiming_Liu]

Hi @SAVIOR 

You can refer below patch about 11x11 evk to solve dependency issue.

Best Regards

Zhiming