We have a leakage problem: our GPIOs are powered before the MCU power banks (see pictures below); the +v3.3_main rail has 2V leakage and as a result, the MCU can't wake up. the SNVS needs to power up before the other rail.
The GPIO pins are powered all the time and we can't change that.
I tried to force the +v3.3_main rail to be 0V, but it changed the GPIOs and affected our design.
since you know better the internal NXP MCU architecture, can you please offer a solution to isolate the +V3.3V_main rail from the GPIOs and solve the leakage problem?
I have attached the design schematics
picture 1, the signals that are powered first: ( connected to 3.3V pull-ups rails that are always up):
picture 2, Are powered after:
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