LPSPI multibyte transfer without CS toggle

[hansung_jung]

Hello,

I use FRAM (Fujitsu, mb85rs1mt) on an I.MX8qxp processor. I run SCLK, MISO, MOSI, CS for SPI connections. But CS doesn't work the way I expect it to.

FRAM is based on fujitsu, mb85rs1mt drivers and operates in compatible mode with jedec, spi-nor drivers.

To read the ID of the FRAM, you must send command bytes and read three more data bytes. The CS must remain low throughout the entire sequence.

However, since CS rises per byte, the ID of FRAM cannot be read because the rising edge interferes with communication.

I found and applied on Google that if I set the CS pin as regular GPIO, I can read the ID of FRAM, but in this case, I can't control the CS pin at all.

The kernel version is 5.10.35, and a custom board is being created and implemented.

[pengyong_zhang]

Hi, @hansung_jung 

You can also test with the latest BSP version.

https://www.nxp.com/design/design-center/software/embedded-software/i-mx-software/embedded-linux-for...

B.R

[pengyong_zhang]

Hi, @hansung_jung 

The config file is empty. Do not need to modify the config file.

Please share your board HW schematic diagram, Have you checked whether the GPIO has been occupied?

B.R

[hansung_jung]

I am sorry that the attached config file had hide property.

Anyway, I understood it does not matter.

Please refer below schematic diagram.

And I checked all gpio but the SPI1_CS0 pin is assigned only for cs.

I think it is very interesting that it works at your board.

I have to search more.

Thanks for your support.

[pengyong_zhang]

Hi, @hansung_jung 

Please refer below code, add the "cs-gpios = <&lsio_gpio1 8 GPIO_ACTIVE_LOW>;" to your dts file.

&lpspi0 {

    fsl,spi-num-chipselects = <1>;

    pinctrl-names = "default";

    pinctrl-0 = <&pinctrl_lpspi0 &pinctrl_lpspi0_cs>;

    cs-gpios = <&lsio_gpio1 8 GPIO_ACTIVE_LOW>;

    status = "okay";

};

I have tested today, cs signal voltage change is no problem. During the data transmission process, it continues to maintain a low level until the data transmission is completed and returns to a high level.

B.R

[hansung_jung]

Thanks for your support, but unfortunetly CS pin does not work.

Refer below scope wave, and my dts file.

Is there anything else I need to check, like .config?

Could you look at my .config just in case?

Please refer the attached file.

[pengyong_zhang]

Hi, @hansung_jung 

Pleae use the following setting to test:

    pinctrl_lpspi0: lpspi0grp {

        fsl,pins = <

            IMX8QXP_SPI0_SCK_ADMA_SPI0_SCK      0x6000040

            IMX8QXP_SPI0_SDO_ADMA_SPI0_SDO      0x6000040

            IMX8QXP_SPI0_SDI_ADMA_SPI0_SDI      0x6000040

        >;

    };

    pinctrl_lpspi0_cs: lpspi0cs {

        fsl,pins = <

            IMX8QXP_SPI0_CS0_LSIO_GPIO1_IO08    0x21

        >;

    };

    pinctrl-0 = <&pinctrl_lpspi0 &pinctrl_lpspi0_cs>;

B.R

[hansung_jung]

Thanks for your solution, however CS does not work.

I attach oscilloscope wave image.

And this is my dts modified as you suggested.

[pengyong_zhang]

Hi, @hansung_jung 

It looks like your settings are correct. I will try to reproduce your problem.

Which dts file are you using? Have you tried using other GPIO as CS?

B.R

[hansung_jung]

Yes, I tried to use other gpio as cs, however it was same result.

Please refer below.

[pengyong_zhang]

Hi, @hansung_jung 

Please share your dts file.

B.R

[hansung_jung]

Thanks for your rapid reply.

I attached my dts file.

[pengyong_zhang]

Hi, @hansung_jung 

when you set the CS pin as regular GPIO.What do you  mean you can't control the CS pin at all? Do you want to control CS level variation during spi communication?

B.R

[hansung_jung]

Looking at the link below, I thought it would be okay to change cs from native control to gpio control.
However, it was confirmed that there was no change at all when the waveform was measured with the cs pin with the oscilloscope when it was changed to gpio control.

Solved: SPI - F-RAM usage on Linux - NXP Community