LPDDR3 read/write latency

[EvenFlow_]

We are using a LPDDR3 memory with write latency 8 and read latency 14 according to the datasheet. The default write/read latency in MX7D_LPDDR3_register_programming_aid_v1_5.xlsx is 6/12 and the Notes says Note, this field is updated automatically and it is not recommended to manually configure it. Can we still update this to 8/14? I am asking because I tried updating it, and the LPDDR3 doesn't seem to work after this.

[pengyong_zhang]

hI @EvenFlow_ 

From the RPA setting, It seems that WL/RL will not change follow the DDR clock change about i.MX7D. 

We are now changing the DDR clock to 420/425 Mhz and are (so far) unable to run stress test tool. Is WL/RL 6/12 OK also at 425 Mhz?

>>>Please share your test fail log.

So, 

[pengyong_zhang]

What do you mean the defalut WL/RL? DDR clock cycle freq at533MHz? 

[EvenFlow_]

The aid has hardcoded WL:6 RL:12 on row 114/115. When we originally ran the stress tool at 533 Mhz, it also gave WL/RL 6/12 so everything matched.

We are now changing the DDR clock to 420/425 Mhz and are (so far) unable to run stress test tool. Is WL/RL 6/12 OK also at 425 Mhz?

[pengyong_zhang]

Hi @EvenFlow_ 

Yes. you are right. You need follow the Stress test result about different DDR frequency point set the RL WL. Do not change it by your self. This may cause unpredictable  DRAM errors.

B.R

[EvenFlow_]

We face some challenges with re-running the stress test tool with the 420 Mhz change on the  product PCB (this quite an old product, etc). Can you say if it is safe to use the default WL/RL from the aid at 420 Mhz PLL_DDR?

[pengyong_zhang]

Hi @EvenFlow_ 

Do not change it by yourself, This important timing parameters is depend on the DDR clock frequency.

 Why are you need to change it?

B.R

[EvenFlow_]

We have a possible HW PCB design flaw in the DDR bus of an existing product and need to lower the DDR bus frequency (528->420 Mhz) as a workaround. As part of this fix we are double checking all timing settings, and it was noticed the read/write latency (on row read/write latency on row 114 and 115 in the spreadsheet) we set in the imx7d does not match the LPDDR3 datasheet. (We have previously run the NXP stress test tool which gave identical settings to what we get from the aid spreadsheet).