LPDDR2 initialization script for i.MX6 solo for

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LPDDR2 initialization script for i.MX6 solo for

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rajeshtripathi
Contributor I

Hello,

Our custom board is using Micron LPDDR2 MT42L128M32D2 chip. USB OTG port is visible and image can be sent over USB downloader but LPDDR2 is not being initialized. Looks the DCD is not correct

Any initialization script available for LPDDR2 fro i.MX6 Solo?

Thanks

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aven_tsao
NXP Employee
NXP Employee

There has a LPDDR2 init script Aid on Compass, you can use it to create LPDDR2 init script.

i.Mx6DQSDL LPDDR2 Script Aid

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aven_tsao
NXP Employee
NXP Employee

There has a LPDDR2 init script Aid on Compass, you can use it to create LPDDR2 init script.

i.Mx6DQSDL LPDDR2 Script Aid

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rajeshtripathi
Contributor I

Thanks a Lot! It worked.

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Yogee
Contributor III

Hi Rajesh,

Please let us know the right settings for LPDDR2 (Single Ch, Single Die with 512MB (4Gb)) on IMX6 Solo. We are not able to make our system work.

Regards

Yogee

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xavierboucher
Contributor III

Hi Yogee.

When I tried to configure LPDDR2, I found 2 things that have to be changed manually after configuring with the aid script.

S2->S4. I guess that you RAM chip is S4 and not S2. By default it is S2 in the aid script and I did not found how to change it. So you have to modify it yourself.

DATA 4    0x021b0018     0x00001688    // MMDC0_MDMISC  - old value 0x00001748 - S2 to S4


CA bus abs delay, this value is always 0 in the aid script but it should not be. Here it is mostly trial and errors. I found out 0x00400000 is a safe value to start with.
DATA 4    0x021b0890      0x00400000  // MMDC0_MPPDCMPR2


If all this failed, you can try to slow down the IMX processor. Maybe the clock is not stabilizing properly.

DATA 4    0x020c8000     0x00013037    //change freq cpu to 660 mhz 0x00013037  //to 1ghz 0x00013052   //800mhz 0x00013021


If you want to find more information about the RAM registers, it is in the IMX6XXRM.pdf in chapter 45.12 MMDC Memory Map/Register Definition.


Also have you tried the DDR stress test? This was very useful to me.

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Yogee
Contributor III

We are able to run the LPDDR2 stress test successfully but not able to boot thru SD card (SD3) port and console with UART3. We did all possible settings.

Please let us know the right settings for SD3 boot (HW boot config is OK) and UART3 console.

Yogee

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aven_tsao
NXP Employee
NXP Employee

HI Yogee:

  1. What kind ddr configuration mode you are using?

          (Please reference to the 2.3 DDR mapping to MMDC controller ports of RM

    • Signal channel mode (32 bit)

Please make sure the DDR Memory Map is “00”, and the ddr start address is “0x10000000”

(Please make sure the memory start address setting is correct in u-boot)

    • Dual channel mode (2 * 32 bit)

Please make sure the DDR Memory Map is “01”, and the ddr start address is “0x80000000”

                  (Please make sure the memory start address setting is correct in u-boot)

          Ps. DDR Memory Map [1:0] is mapping to BOOT_CFG3[5:4]

     2. Please measurement the SD3_CLK and SD3_CMD signal to check the Boot mode settings are correct

          (If the boot mode settings are correct, the ROM will try to access the SD3)

          Ps. Please reference to chapter 8 system boot in RM for the boot configure settings if boot mode incorrect

     3. The default debug UART port is UART1 in FSL BSP, please check the UART1_TXD (CSI0_DAT10)to clarify u-boot status.   

Best regards

Aven

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mcyoyan
Contributor I

We are looking for a complete uboot compiled for a IMX6 solo and a Micron 128 mB LPDDR2 to test our new custom board. We want to be sure our design is well done. Somebody can help us ?

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Yogee
Contributor III

Dear Rajesh,

Could you please let me know if you have followed bit swapping within byte of LPDDR2 while interfacing with IMX6.

Yogee

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