i.MX6 CCM and PLL setting by DCD.

[satoshishimoda]

Hi community,

Our partner tried setting CCM and PLL by DCD with i.MX6DL L3.0.35_4.1.0 BSP.

However, i.MX6DL did not boot when CCD and PLL are set by DCD even though DCD can set CCM and PLL as Table 8-33 in IMX6SDLRM Rev.1.

So we want to know whether there is some restrict to set CCM by DCD.

Could you let me kwnow it?

Or could you send a sample DCD to set CCM and PLL?

Best Regards,

Satoshi Shimoda

[fabio_estevam]

In DCD table only register writes are allowed. However for enabling the PLL you would also need to poll the "PLL lock" bit.

So I would recommend you to activate the PLL in C code instead of doing it inside the DCD table.

As a reference you could check the "_clk_pll_enable" function from the kernel:

http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/arch/arm/mach-mx6/clock.c?h=imx_3.0...

, and implement the same in your bootloader.

[Yuri]

Some polling options are available for i.MX6, using "Check Data Command". Please refer to section

8.6.2.2 (Check Data Command) of i.MX6 SDL RM.

[Yuri · Accepted solution]

  The CCM address area is allowed for the DCD, according to Table 8-33 (Valid DCD Address Ranges)
of the i.MX6 SDL RM. Another way, that we should take into account recommendations of section 18.5.1.6
(Disabling / Enabling PLLs).

   Also, please take a look at

Re: How to modify Bootloader and kernel to support LPDDR2?

Have a great day,
Yuri

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