L6.6, sn65dsi83 Error:

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L6.6, sn65dsi83 Error:

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2,933件の閲覧回数
pavelko
Contributor III

I'm trying to make sn65dsi84 dsi2lvds bridge working with Linux kernel 6.6.52 (Yocto scartgap).

After fixing problems with attaching mipi-dsi to SN65DSI83 driver: IMX8MM-sn65dsi83-yocto-scarthgap-mipi-dsi-is-not-initialized 

and correcting LVDS timing parameters in DT: Error-Cannot-find-any-crtc-or-sizes -

facing another problem: seems that MIPI-DSI is not sending data:

SN65DSI83driver cannot lock PLL because it has DSI source clock.

[    2.946302] sn65dsi83 0-002c: failed to lock PLL, ret=-110

 

my devicetree is:

/dts-v1/;

#include "imx8mm.dtsi"

/ {
	panel: panel10inch {
		width-mm = <210>;
		height-mm = <157>;
		compatible = "panel-lvds";
		backlight = <&bl_lcd>;
		data-mapping = "vesa-24";
		status = "okay";
		enable-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; 

		panel-timing {
			clock-frequency = <65000000>;
			hactive = <1024>;
			vactive = <768>;
			/* */
			hfront-porch = <40>;
			hsync-len = <60>;
			hback-porch = <220>;
			/* */
			vfront-porch = <7>;
			vsync-len = <10>;
			vback-porch = <21>;
			/* */
			vsync-active = <0>;
			hsync-active = <0>;
			de-active = <1>;
			pixelclk-active = <0>;
		};

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;

				panel_in: endpoint {
					remote-endpoint = <&bridge_out>;
				};
			};
		};
	};
};

&i2c1 {
	dsi_lvds_bridge: sn65dsi84@2c {
		compatible = "ti,sn65dsi83";
		reg = <0x2c>;
		enable-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; 
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_dsi_bridge>;
		vcc-supply = <&reg_1V8>;
		status = "okay";
		of-depends-on = <&panel>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;

				bridge_in: endpoint {
					remote-endpoint = <&mipi_dsi_out>;
					data-lanes = <1 2 3 4>;
				};
			};

			port@2 {
				reg = <2>;

				bridge_out: endpoint {
					remote-endpoint = <&panel_in>;
				};
			};
		};
	};
};

&lcdif {
	status = "okay";
};

&mipi_dsi {
	status = "okay";

	port@1 {
		mipi_dsi_out: endpoint {
			remote-endpoint = <&bridge_in>;
			data-lanes = <1 2 3 4>;
			/*lane-polarities = <1 0 0 0 0>;*/
			attach-bridge;
		};
	};
};

 

bootlog is attached.

0 件の賞賛
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1 解決策
2,923件の閲覧回数
pavelko
Contributor III

Found strange thing:

[    2.946302] sn65dsi83 0-002c: failed to lock PLL, ret=-110
[    2.948106] imx_sec_dsim_drv 32e10000.mipi_dsi: imx_sec_dsim_encoder_atomic_enable: Enter
[    2.951027] sn65dsi83 0-002c: sn65dsi83_atomic_enable: Enter
[    2.956980] sn65dsi83 0-002c: Unexpected link status 0x01

 

The sn65dsi83 probe function pries to lock PLL from MIPI-DSI before imx_sec_dsim_encoder_atomic_enable() function ensbles it.

Moved piece of code that sets PLL to sn65dsi83_atomic_enable() function.

Works now!

 

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0 件の賞賛
返信
2 返答(返信)
2,924件の閲覧回数
pavelko
Contributor III

Found strange thing:

[    2.946302] sn65dsi83 0-002c: failed to lock PLL, ret=-110
[    2.948106] imx_sec_dsim_drv 32e10000.mipi_dsi: imx_sec_dsim_encoder_atomic_enable: Enter
[    2.951027] sn65dsi83 0-002c: sn65dsi83_atomic_enable: Enter
[    2.956980] sn65dsi83 0-002c: Unexpected link status 0x01

 

The sn65dsi83 probe function pries to lock PLL from MIPI-DSI before imx_sec_dsim_encoder_atomic_enable() function ensbles it.

Moved piece of code that sets PLL to sn65dsi83_atomic_enable() function.

Works now!

 

0 件の賞賛
返信
2,916件の閲覧回数
pavelko
Contributor III
 
0 件の賞賛
返信
%3CLINGO-SUB%20id%3D%22lingo-sub-2075942%22%20slang%3D%22en-US%22%20mode%3D%22CREATE%22%3EL6.6%2C%20sn65dsi83%20Error%3A%3C%2FLINGO-SUB%3E%3CLINGO-BODY%20id%3D%22lingo-body-2075942%22%20slang%3D%22en-US%22%20mode%3D%22CREATE%22%3E%3CP%3E%E7%A7%81%E3%81%AFsn65dsi84%20dsi2lvds%E3%83%96%E3%83%AA%E3%83%83%E3%82%B8%E3%82%92Linux%E3%82%AB%E3%83%BC%E3%83%8D%E3%83%AB6.6.52(Yocto%20scartgap)%E3%81%A7%E5%8B%95%E4%BD%9C%E3%81%95%E3%81%9B%E3%82%8B%E3%82%88%E3%81%86%E3%81%AB%E3%81%97%E3%82%88%E3%81%86%E3%81%A8%E3%81%97%E3%81%A6%E3%81%84%E3%81%BE%E3%81%99%E3%80%82%3C%2FP%3E%3CP%3Emipi-dsi%E3%82%92SN65DSI83%E3%83%89%E3%83%A9%E3%82%A4%E3%83%90%E3%83%BC%E3%81%AB%E3%82%A2%E3%82%BF%E3%83%83%E3%83%81%E3%81%99%E3%82%8B%E9%9A%9B%E3%81%AE%E5%95%8F%E9%A1%8C%E3%82%92%E4%BF%AE%E6%AD%A3%E3%81%97%E3%81%9F%E5%BE%8C%3A%20%3CA%20href%3D%22https%3A%2F%2Fcommunity.nxp.com%2Ft5%2Fi-MX-Processors%2FIMX8MM-sn65dsi83-yocto-scarthgap-mipi-dsi-is-not-initialized%2Fm-p%2F2031234%22%20target%3D%22_self%22%3EIMX8MM-sn65dsi83-yocto-scarthgap-mipi-dsi-is-not-initialized%3C%2FA%3E%26nbsp%3B%3C%2FP%3E%3CP%3EDT%20%E3%81%AE%20LVDS%20%E3%82%BF%E3%82%A4%E3%83%9F%E3%83%B3%E3%82%B0%20%E3%83%91%E3%83%A9%E3%83%A1%E3%83%BC%E3%82%BF%E3%81%AE%E4%BF%AE%E6%AD%A3%3A%20%3CA%20href%3D%22https%3A%2F%2Fcommunity.nxp.com%2Ft5%2Fi-MX-Processors%2Fimx8mm-L6-6-sn65dsi83-Error-Cannot-find-any-crtc-or-sizes%2Fm-p%2F2073620%22%20target%3D%22_self%22%3EError-Cannot-find-any-crtc-or-sizes%3C%2FA%3E%20-%3C%2FP%3E%3CP%3E%E5%88%A5%E3%81%AE%E5%95%8F%E9%A1%8C%E3%81%AB%E7%9B%B4%E9%9D%A2%E3%81%97%E3%81%A6%E3%81%84%E3%82%8B%3AMIPI-DSI%E3%81%8C%E3%83%87%E3%83%BC%E3%82%BF%E3%82%92%E9%80%81%E4%BF%A1%E3%81%97%E3%81%A6%E3%81%84%E3%81%AA%E3%81%84%E3%82%88%E3%81%86%E3%81%A7%E3%81%99%E3%80%82%3C%2FP%3E%3CP%3ESN65DSI83driver%20%E3%81%AF%20DSI%20%E3%82%BD%E3%83%BC%E3%82%B9%20%E3%82%AF%E3%83%AD%E3%83%83%E3%82%AF%E3%81%8C%E3%81%82%E3%82%8B%E3%81%9F%E3%82%81%E3%80%81PLL%20%E3%82%92%E3%83%AD%E3%83%83%E3%82%AF%E3%81%A7%E3%81%8D%E3%81%BE%E3%81%9B%E3%82%93%E3%80%82%3C%2FP%3E%3CPRE%20class%3D%22lia-code-sample%20language-markup%22%3E%3CCODE%20translate%3D%22no%22%3E%5B%20%20%20%202.946302%5D%20sn65dsi83%200-002c%3A%20failed%20to%20lock%20PLL%2C%20ret%3D-110%3C%2FCODE%3E%3C%2FPRE%3E%3CBR%20%2F%3E%3CP%3E%E7%A7%81%E3%81%AEdevicetree%E3%81%AF%3A%3C%2FP%3E%3CPRE%20class%3D%22lia-code-sample%20language-c%22%3E%3CCODE%20translate%3D%22no%22%3E%2Fdts-v1%2F%3B%0A%0A%23include%20%22imx8mm.dtsi%22%0A%0A%2F%20%7B%0A%09panel%3A%20panel10inch%20%7B%0A%09%09width-mm%20%3D%20%26lt%3B210%26gt%3B%3B%0A%09%09height-mm%20%3D%20%26lt%3B157%26gt%3B%3B%0A%09%09compatible%20%3D%20%22panel-lvds%22%3B%0A%09%09backlight%20%3D%20%26lt%3B%26amp%3Bbl_lcd%26gt%3B%3B%0A%09%09data-mapping%20%3D%20%22vesa-24%22%3B%0A%09%09status%20%3D%20%22okay%22%3B%0A%09%09enable-gpios%20%3D%20%26lt%3B%26amp%3Bgpio1%2014%20GPIO_ACTIVE_HIGH%26gt%3B%3B%20%0A%0A%09%09panel-timing%20%7B%0A%09%09%09clock-frequency%20%3D%20%26lt%3B65000000%26gt%3B%3B%0A%09%09%09hactive%20%3D%20%26lt%3B1024%26gt%3B%3B%0A%09%09%09vactive%20%3D%20%26lt%3B768%26gt%3B%3B%0A%09%09%09%2F*%20*%2F%0A%09%09%09hfront-porch%20%3D%20%26lt%3B40%26gt%3B%3B%0A%09%09%09hsync-len%20%3D%20%26lt%3B60%26gt%3B%3B%0A%09%09%09hback-porch%20%3D%20%26lt%3B220%26gt%3B%3B%0A%09%09%09%2F*%20*%2F%0A%09%09%09vfront-porch%20%3D%20%26lt%3B7%26gt%3B%3B%0A%09%09%09vsync-len%20%3D%20%26lt%3B10%26gt%3B%3B%0A%09%09%09vback-porch%20%3D%20%26lt%3B21%26gt%3B%3B%0A%09%09%09%2F*%20*%2F%0A%09%09%09vsync-active%20%3D%20%26lt%3B0%26gt%3B%3B%0A%09%09%09hsync-active%20%3D%20%26lt%3B0%26gt%3B%3B%0A%09%09%09de-active%20%3D%20%26lt%3B1%26gt%3B%3B%0A%09%09%09pixelclk-active%20%3D%20%26lt%3B0%26gt%3B%3B%0A%09%09%7D%3B%0A%0A%09%09ports%20%7B%0A%09%09%09%23address-cells%20%3D%20%26lt%3B1%26gt%3B%3B%0A%09%09%09%23size-cells%20%3D%20%26lt%3B0%26gt%3B%3B%0A%0A%09%09%09port%400%20%7B%0A%09%09%09%09reg%20%3D%20%26lt%3B0%26gt%3B%3B%0A%0A%09%09%09%09panel_in%3A%20endpoint%20%7B%0A%09%09%09%09%09remote-endpoint%20%3D%20%26lt%3B%26amp%3Bbridge_out%26gt%3B%3B%0A%09%09%09%09%7D%3B%0A%09%09%09%7D%3B%0A%09%09%7D%3B%0A%09%7D%3B%0A%7D%3B%0A%0A%26amp%3Bi2c1%20%7B%0A%09dsi_lvds_bridge%3A%20sn65dsi84%402c%20%7B%0A%09%09compatible%20%3D%20%22ti%2Csn65dsi83%22%3B%0A%09%09reg%20%3D%20%26lt%3B0x2c%26gt%3B%3B%0A%09%09enable-gpios%20%3D%20%26lt%3B%26amp%3Bgpio1%2012%20GPIO_ACTIVE_HIGH%26gt%3B%3B%20%0A%09%09pinctrl-names%20%3D%20%22default%22%3B%0A%09%09pinctrl-0%20%3D%20%26lt%3B%26amp%3Bpinctrl_dsi_bridge%26gt%3B%3B%0A%09%09vcc-supply%20%3D%20%26lt%3B%26amp%3Breg_1V8%26gt%3B%3B%0A%09%09status%20%3D%20%22okay%22%3B%0A%09%09of-depends-on%20%3D%20%26lt%3B%26amp%3Bpanel%26gt%3B%3B%0A%0A%09%09ports%20%7B%0A%09%09%09%23address-cells%20%3D%20%26lt%3B1%26gt%3B%3B%0A%09%09%09%23size-cells%20%3D%20%26lt%3B0%26gt%3B%3B%0A%0A%09%09%09port%400%20%7B%0A%09%09%09%09reg%20%3D%20%26lt%3B0%26gt%3B%3B%0A%0A%09%09%09%09bridge_in%3A%20endpoint%20%7B%0A%09%09%09%09%09remote-endpoint%20%3D%20%26lt%3B%26amp%3Bmipi_dsi_out%26gt%3B%3B%0A%09%09%09%09%09data-lanes%20%3D%20%26lt%3B1%202%203%204%26gt%3B%3B%0A%09%09%09%09%7D%3B%0A%09%09%09%7D%3B%0A%0A%09%09%09port%402%20%7B%0A%09%09%09%09reg%20%3D%20%26lt%3B2%26gt%3B%3B%0A%0A%09%09%09%09bridge_out%3A%20endpoint%20%7B%0A%09%09%09%09%09remote-endpoint%20%3D%20%26lt%3B%26amp%3Bpanel_in%26gt%3B%3B%0A%09%09%09%09%7D%3B%0A%09%09%09%7D%3B%0A%09%09%7D%3B%0A%09%7D%3B%0A%7D%3B%0A%0A%26amp%3Blcdif%20%7B%0A%09status%20%3D%20%22okay%22%3B%0A%7D%3B%0A%0A%26amp%3Bmipi_dsi%20%7B%0A%09status%20%3D%20%22okay%22%3B%0A%0A%09port%401%20%7B%0A%09%09mipi_dsi_out%3A%20endpoint%20%7B%0A%09%09%09remote-endpoint%20%3D%20%26lt%3B%26amp%3Bbridge_in%26gt%3B%3B%0A%09%09%09data-lanes%20%3D%20%26lt%3B1%202%203%204%26gt%3B%3B%0A%09%09%09%2F*lane-polarities%20%3D%20%26lt%3B1%200%200%200%200%26gt%3B%3B*%2F%0A%09%09%09attach-bridge%3B%0A%09%09%7D%3B%0A%09%7D%3B%0A%7D%3B%3C%2FCODE%3E%3C%2FPRE%3E%3CBR%20%2F%3E%3CP%3Ebootlog%20%E3%81%8C%E6%B7%BB%E4%BB%98%E3%81%95%E3%82%8C%E3%81%A6%E3%81%84%E3%81%BE%E3%81%99%E3%80%82%3C%2FP%3E%3C%2FLINGO-BODY%3E%3CLINGO-SUB%20id%3D%22lingo-sub-2075981%22%20slang%3D%22en-US%22%20mode%3D%22CREATE%22%3ERe%3A%20L6.6%2C%20sn65dsi83%20Error%3A%3C%2FLINGO-SUB%3E%3CLINGO-BODY%20id%3D%22lingo-body-2075981%22%20slang%3D%22en-US%22%20mode%3D%22CREATE%22%3E%3CP%3E%E5%A5%87%E5%A6%99%E3%81%AA%E3%82%82%E3%81%AE%E3%82%92%E8%A6%8B%E3%81%A4%E3%81%91%E3%81%BE%E3%81%97%E3%81%9F%3A%3C%2FP%3E%3CP%3E%3CSPAN%3E%5B%26nbsp%3B%26nbsp%3B%26nbsp%3B%202.946302%5Dsn65dsi83%200-002c%3A%20PLL%20%E3%81%AE%E3%83%AD%E3%83%83%E3%82%AF%E3%81%AB%E5%A4%B1%E6%95%97%E3%81%97%E3%81%BE%E3%81%97%E3%81%9F%E3%80%82ret%3D-110%3CBR%20%2F%3E%5B%26nbsp%3B%26nbsp%3B%26nbsp%3B%202.948106%5Dimx_sec_dsim_drv%2032e10000.mipi_dsi%3Aimx_sec_dsim_encoder_atomic_enable%3A%20%E5%85%A5%E5%8A%9B%3CBR%20%2F%3E%5B%26nbsp%3B%26nbsp%3B%26nbsp%3B%202.951027%5DSN65DSI83%200-002C%3Asn65dsi83_atomic_enable%3A%E5%85%A5%E5%8A%9B%3CBR%20%2F%3E%5B%26nbsp%3B%26nbsp%3B%26nbsp%3B%202.956980%5Dsn65dsi83%200-002c%3A%20%E4%BA%88%E6%9C%9F%E3%81%97%E3%81%AA%E3%81%84%E3%83%AA%E3%83%B3%E3%82%AF%20%E3%82%B9%E3%83%86%E3%83%BC%E3%82%BF%E3%82%B9%200x01%3C%2FSPAN%3E%3C%2FP%3E%3CBR%20%2F%3E%3CP%3E%3CSPAN%3Esn65dsi83%20%E3%83%97%E3%83%AD%E3%83%BC%E3%83%96%E9%96%A2%E6%95%B0%E3%81%AF%E3%80%81imx_sec_dsim_encoder_atomic_enable()%20%E9%96%A2%E6%95%B0%E3%81%8C%20PLL%20%E3%82%92%E3%82%A8%E3%83%B3%E3%82%B9%E3%83%96%E3%83%AB%E3%81%99%E3%82%8B%E5%89%8D%E3%81%AB%E3%80%81MIPI-DSI%20%E3%81%8B%E3%82%89%20PLL%20%E3%82%92%E3%83%AD%E3%83%83%E3%82%AF%E3%81%97%E3%81%BE%E3%81%99%E3%80%82%3C%2FSPAN%3E%3C%2FP%3E%3CP%3E%3CSPAN%3EPLL%20%E3%82%92%20sn65dsi83_atomic_enable()%20%E9%96%A2%E6%95%B0%E3%81%AB%E8%A8%AD%E5%AE%9A%E3%81%99%E3%82%8B%E3%82%B3%E3%83%BC%E3%83%89%E3%82%92%E7%A7%BB%E5%8B%95%E3%81%97%E3%81%BE%E3%81%97%E3%81%9F%E3%80%82%3C%2FSPAN%3E%3C%2FP%3E%3CP%3E%3CSPAN%3E%E4%BB%8A%E3%81%99%E3%81%90%E5%8B%95%E4%BD%9C%E3%81%97%E3%81%BE%E3%81%99!%3C%2FSPAN%3E%3C%2FP%3E%3CBR%20%2F%3E%3C%2FLINGO-BODY%3E