Is there a limitation of the Length field in the Boot Data to do XIP with QSPI flash?

取消
显示结果 
显示  仅  | 搜索替代 
您的意思是: 

Is there a limitation of the Length field in the Boot Data to do XIP with QSPI flash?

636 次查看
SSE-Sak
Contributor I

Hi NXP team,

 

I tried XIP from QSPI flash in the custom board that has a i.MX6UL and a external QSPI flash.

I set the IVT and Boot Data as shown below.

    IVT.entry = 0x60002000;    // entry address is within QSPI address range in the CPU memory map.

    BootData.start = 0x60000000;    // Set the start address of QSPI address range to specify XIP.

    BootData.length = 0;    // I think that the length is not required for XIP?

But XIP was not achieved. It seemed to not branch to the IVT.entry and stay in the Boot ROM program.

So I changed the length field to non-zero number for example 0x10000 for trial. Then I succeeded XIP with QSPI. 

At the result of more trial, I found that the length field in the Boot Data with value of equal or greater than 0x20 is required to achieve XIP on QSPI flash.

Although I read Reference Manual and Errata document of i.MX6UL, I didn't find this limitation notice.

Is it described anywhere?

Is this limitation a new Errata?

 

Thanks.

0 项奖励
回复
11 回复数

603 次查看
Zhiming_Liu
NXP TechSupport
NXP TechSupport

Hi,

BootData.length here is the size of boot image, it should be the real size of boot image.

Zhiming_Liu_0-1760145131248.png

 

Please keep BootData.length non‑zero and set it to the actual image size.

Best Regards,
Zhiming

0 项奖励
回复

516 次查看
SSE-Sak
Contributor I
Hi NXP TechSupport,



Thank you for responding to my question.

Is my understanding correct that

1. The Boot ROM judges with BootData.length if the boot image exists or not.

2. And does not jump to IVT.entry if the boot image does not exist (i.e. BootData.lengyh is less than 32 bytes).

If this is correct, these Boot ROM's behavior are specific to i.MX6UL? Or is it the same for other SoC?



Best regards,
0 项奖励
回复

511 次查看
Zhiming_Liu
NXP TechSupport
NXP TechSupport

Hi,

Yes, your understanding are correct. It's similiar for other SOC, the image should be vaild, then ROM handle it.

Best Regards,
Zhiming

0 项奖励
回复

472 次查看
SSE-Sak
Contributor I
Hi NXP TechSupport,

Thank you for your answer.
However the other custom board which has a i.MX6solo and a external parallel NOR Flash memory connected via EIM that contains application program could run XIP mode although setting BootData.length = 0.
Please let me know why i.MX6solo can run XIP even if BootData.length = 0.

Best regards,
SSE-Sak
0 项奖励
回复

369 次查看
Zhiming_Liu
NXP TechSupport
NXP TechSupport

Hi,

Does the i.MX6ULL also use EIM?

Best Regards,
Zhiming

0 项奖励
回复

364 次查看
Zhiming_Liu
NXP TechSupport
NXP TechSupport

If the boot device are different, ROM may handle them differently. However, the issue you mentioned with the i.MX6Solo does indeed go beyond what the manual can explain.

0 项奖励
回复

358 次查看
SSE-Sak
Contributor I
Hi NXP TechSupport,

Yes the boot device are different.
I was thinking that the BootData.length is only required in non-XIP mode to decide the coping size of the boot image from boot device to DDR or OCRAM.
But, if the BootData.length is also used to determine whether the Boot ROM should jump to IVT.entry, is the i.MX6solo behavior that can boot in XIP mode via EIM with BootData.length = 0 a new errata?

Best regards,
0 项奖励
回复

244 次查看
Zhiming_Liu
NXP TechSupport
NXP TechSupport

Hi 

Can you share which OS you are using ?  Did you writing "IVT and boot data" by own tools or NXP tool?

Best Regards,
Zhiming

0 项奖励
回复

293 次查看
Zhiming_Liu
NXP TechSupport
NXP TechSupport

Hi @SSE-Sak 

I need confirm with internal team, not sure if this is a errata or the ROM itself is designed this way


Best Regards,
Zhiming

0 项奖励
回复

201 次查看
SSE-Sak
Contributor I
Hi NXP TechSupport,

I cannot disclose OS because I'm not in a position to decide sharing details.
I do not use those tools to write IVT and Boot Data. I write IVT and Boot Data as a const table with specific #pragma section in my source code and I write these data to QSPI Flash memory using scatter-loading mechanism so that these section (IVT first) are located in 0x1000 offset from QSPI Flash ROM start address.
So, I don't think OS is relevant.

Best regards,
SSE-Sak
0 项奖励
回复

48 次查看
Zhiming_Liu
NXP TechSupport
NXP TechSupport

Hi,

I checked with internal team,  doubt that you may use 6Solo chip version may be old,   and on old version chip sample,  ROM code not check that bootdata.length. Please dump 0x00000048 address contents on 6Solo

Best Regards,
Zhiming

0 项奖励
回复