If we consider i.MX7, which consist of Cortex A7 and Cortex-M4; in section 4.2.1 (Overview)
of i.MX 7Dual r Reference Manual, Rev. 1, 01/2018:
"The Cortex-M4 implementation includes two tightly-coupled local memories and two cache
memories connected to these bus interfaces although the device implementation connects
to the 64-bit system bus interconnect and supports a 32-byte cache line size.
• L1 2-way set-associative 16 KB Instruction/Data cache with 32B line size length ..."