I want to know if there is a cache inside the ARM Cortex-M4.
I did not find any clue in the technical reference manual, but is that official or hidden? I know that some microcontrollers have a cache, but then it's between the bus and the RAM, not inside the core.
Do you know of any document that clarifies this?
Hello,
If we consider i.MX7, which consist of Cortex A7 and Cortex-M4; in section 4.2.1 (Overview)
of i.MX 7Dual r Reference Manual, Rev. 1, 01/2018:
"The Cortex-M4 implementation includes two tightly-coupled local memories and two cache
memories connected to these bus interfaces although the device implementation connects
to the 64-bit system bus interconnect and supports a 32-byte cache line size.
• L1 2-way set-associative 16 KB Instruction/Data cache with 32B line size length ..."
Regards,
Yuri.