Is it possible to configure the SSI Interconnect in the i.MX 8QuadMax?

[NicolasVS]

Dear NXP Community,

In the i.MX 8QuadMax Reference Manual (Rev. 0, 9/2021), the section 1.2.1.2 states that "the DRAM Block (DB) is the big switch in the [i.MX 8QM] system. [...] Each subsystem is connected to the DB by a point-to-point SSI (Source Synchronous Interface) link. [...] The System Traffic Controller (STC) is in charge of shaping traffic coming out of a subsystem and updating their QoS".

Is there a way to configure the SSI (especially the STC)?
If not, is there a way to monitor the "Big Node Arbiter" (please see the figure 3-1), for example to detect congestion or any failures?

Thank you in advance.

Nicolas

[NicolasVS]

Thank you very much Joseph for your fast and concise reply!

Is there further documentation available about this SSI interconnect, perhaps under a non-disclosure agreement?

[JosephAtNXP]

Hi,

The department is interested in a more specific subject. Could you clarify in more detail what are you trying to optimize (particular use case, subsystems involved etc.)? Perhaps then the team would be able to provide a more focused guidance.

Regards

[JosephAtNXP]

Hi,

Let me see if there are any documents that can explain the module.

Regards,

[JosephAtNXP]

Hi,

Thank you for your interest in NXP Semiconductor products,

Please excuse the late reply,

The SSI is a point to point structure – it takes the 5 AXI channels and muxes them onto two transport layers – there is no high level arbitration – simply allows the write data and ra/wa to overlap on the same wires (RA > WA > WDATA)

SCT does mux as told by you; which acts as a distributed arbiter over 4 channels – choosing the 3 highest priority, following a QoS based priority arbiter.

In conclusion, the IP handles congestion based on QoS and there shouldn't be any congestion that the module can not be able to handle.

Regards