Is i.MX28 MMU enabled during DDR test in the IMX_OBDS?

[torus1000]

Hi,

I would like to try DDR test in the IMX_OBDS for my custom i.MX28 board.

Is the MMU/d-cache enabled during DDR test of OBDS?

OBDS: On-Board Diagnostic Suit for the i.MX28(REV 1)
https://www.nxp.com/webapp/sps/download/license.jsp?colCode=IMX_OBDS

In addition,

I found following descriptions in the i.MX28 reference manual;

- To accelerate the boot process, the MMU/d-cache is enabled during the time consuming
HAB authentication process (RSA).

- MMU and D-Cache are enabled in default to speed up HAB functions
execution speed.

Is the MMU/d-cache enabled during normal boot?

Can someone help me?

[igorpadykov · Accepted solution]

Hi torus1000

>Is the MMU/d-cache enabled during DDR test of OBDS?

no

>Is the MMU/d-cache enabled during normal boot?

mmu is configured by fuse HW_OCOTP_ROM7:0x8002C210:1 MMU_DISABLE

described in Table 12-9. General ROM Bit in ROM7 OCOTP Bank

i.MX28 Reference Manual

https://www.nxp.com/docs/en/reference-manual/MCIMX28RM.pdf

Best regards
igor
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