Hello,
In synchronous mode, after address assertion, a burst of sequential
data can be accessed, assuming address incrementing is provided
by an external device (internally). Start address of the burst is provided
by i.MX6 master. Burst length is configured in EIM. From section 22.5.4
(Burst Mode (Synchronous) Memory Operation) of the i.MX6 S/DL RM :
“When this mode is set, the controller attempts to translate the Master burst
accesses to memory burst accesses, being limited by the memory burst length,
predefined by BL value, or memory and Master WRAP/INCR boundary crossing
non-matching. Only the first address accessed is put by the controller on the external
address bus in a memory burst sequence.”
The continuous mode is differ from single burst in such manner that
the clock is not stopped right after burst finish.
Have a great day,
Yuri
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