Interface error occur of MOST of i.MX6Dual.

[takashitakahash]

Dear community.

Our customer has question of MOST.

Events such as the following have been occurred in the MOST MediaLB communication (6pin specification).

Therefore, in iMX6D side, Would you please advice errata and related to the MOST communication of the DIG / DAT early 1bit.

We wish advice on factors that would send the DIG / DAT 1bit early.

Customer are using the same line in the transmission and reception, artwork factors are thought to be small.

Thank you,

Best.

[jimmychan]

I got the reply from the expert.

RD team also mention this issue may caused by not correctly clearing the bypass bit of the CCM_ANALOG_PLL_MLBn register. Is any feedback/update from customer for clearing/modify the "CCM_ANALOG_PLL_MLBn"?

[jimmychan]

There is a register "RX_CLK_DELAY_CFG" of "CCM_ANALOG_PLL_MLBn" can controls the clock delay of RX  side, can you try to adjust it to see what happen? thanks.