Imx8mp + ST7703 correctly scheduled but nothing in output

[Tang_]

Hello everyone,

I'm currently trying to enable the MIPI-DSI display based on the Imx8mp Variscite board.

Hoping that someone can help me.

I'm using the following setup : 

• Driver : panel-sitronix-st7703.c updated regarding the TFT (based on a ST7703 controller)
• DST : imx8mp-var-dart-dt8mcustomboard.dts updated

Previously I updated the DTS for another TFT, and then using an other controler HX8394.

Using a MIPI analyzer (LA5076 and oscilloscope) I'm able to check that the driver ; HX8394, was correctly scheduled and the right behavior during the init phase (during the LP mode) :

By switching to the ST7703, I'm not able to catch the init sequence in output (using the same analyzer as previoulsy).

I can see that the driver is correctly called and additing some debugging instruction I can see that the frame are correctly built : 

[    0.078755] platform 32e80000.lcd-controller: Fixing up cyclic dependency with 32e60000.mipi_dsi
[    2.147933] imx_sec_dsim_drv 32e60000.mipi_dsi: version number is 0x1060200
[    2.160420] panel-sitronix-st7703 32e60000.mipi_dsi.0: 640x960@99 24bpp dsi 4dl - ready
[    2.170998] imx-drm display-subsystem: bound 32e60000.mipi_dsi (ops imx_sec_dsim_ops)

In addition what the DTS looks like (I kept the HX8394 names, as I previously used the HX8394, I only changed the compatible line) :

&mipi_dsi {
status = "okay";

panel@0 {
compatible = "xingbangda,xbd599";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hx8394>;
himax,dsi-lanes = <4>;
enable-gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>; /* DT8MCustomBoard J25.2 */
reset-gpios = <&gpio4 1 GPIO_ACTIVE_LOW>; /* DT8MCustomBoard J25.4 */
vcc-supply = <&reg_hx8394_vcc>;
iovcc-supply = <&reg_hx8394_iovcc>;
backlight = <&backlight>;
status = "okay";
};

};

[joanxie]

you can refer to the link as below

https://community.nxp.com/t5/i-MX-Processors/how-to-add-a-new-panel-with-imx8mm-evk-I-got-some-probl...

let me remind, try to add this in your driver dsi->mode_flags |= MIPI_DSI_MODE_LPM;

[Tang_]

Hello Joanxie,

Thank you very much for your help, by changing the following lines : 

static const struct st7703_panel_desc xbd599_desc = {
        .mode = &xbd599_mode,
        .lanes = 4,
        .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | MIPI_DSI_MODE_LPM,
        .format = MIPI_DSI_FMT_RGB888,
        .init_sequence = xbd599_init_sequence,
};

Adding the flag MIPI_DSI_MODE_LPM, I'm able now to see the init sequence, below a screenshot from the power-up : 

One thing that remains strange : I am not able to see the clock...

Any idea ?

[Tang_]

To keep you updated

I finaly found where was my issue, the analyzer had a wrong setting and had a too high threshold during the HS mode (lowest value compare to the LP mode)
I can now sample the signals even if I'm not able to detail the frame due to the bandwidth.

I'm able to verify the good behavior during the init sequence and afterward by changing as well the values in the drm_display_mode structure to display something on the screen.

But for now I still have some lines, that you can see here, over the picture :

I guess it's coming from the timing setting as well, maybe the clock (in the drm_display_mode), but even by setting the following value I still have this issue : 

clock = (H Total x V Total x 60) / 1000

Am I wrong with the clock value ? Or could it from somewhere else ?

[joanxie]

pixel clock = (hactive + hfront_porch + hsync_len + hback_porch) x (vactive + vfront_porch + vsync_len + vback_porch) x frame rate

bit_clk = pixel clock * bits per pixel / number of lanes

[Tang_]

Hi Joanxie

Thank you very much for your feedback.

Does it clock in the drm_display_mode structure is the bit clock or the pixel clock ?

[joanxie]

yes, in fact you can refer to the definition of this structure, it's clear

https://github.com/nxp-imx/linux-imx/blob/lf-6.1.y/include/drm/drm_modes.h#L252

struct drm_display_mode {
/**
* @clock:
*
* Pixel clock in kHz.
*/
int clock; /* in kHz */

[Tang_]

Hi Joanxie,

Thank you very much, that's clear.

After discussion with the TFT supplier, I made some tests using clock from 29998 until 40000 and higher, conclusion : and from 29998 until 39000 I have the result shown just before : desktop with horizontal lanes.

Using 40000, the TFT has a different behavior, the screen is blinking, the desktop is shown but with a lot of "perturbations".

From what I have the pixel clock should be 39998KHz ... 

Any advices from your side ?

[joanxie]

for imx8mp mipi dsi, can support up to 6Gbps, if the format is 24bpp, the pixel clock can be supported up to 250M, you check if you set timings correct or not, pls refer to the enclosed application note to debug step by step

[Tang_ · Accepted solution]

I think we can close this topic as it is, as we are discussing something different compare to the original topic.

To sum-up : By changing the timing setting, the flags field too and correctly setting the trigger on the analyzer, I'm able now to display something on the screen.

The content of the screen is not clearlyt shown (horizontal lines over the real desktop)

Investigation on going