We've developed a new board around the imx8mm. We're using two i2c busses both at 400khz. This board connects to a second board via a cable approximately 8cm long. This cable has both i2c busses as well as 5v and some Io interrupts.
We've been chasing an apparent i2c bug for a number of weeks which results in failed transactions (normally reads) on both busses.
We've worked on capacitance, slew rate, levels etc and from our scope both busses look almost perfect. We can't see anything that could cause issues. No coupling or interference between buseses etc.
The effect of the issue seems to cause the CPU to send fewer clock cycles than required, resulting in failed transactions. We can make the issue worse by connecting cables (even interminated open-ended cables) to the main board. This suggests interference or grounding but as I said, we can't see anything on the scope.
Any ideas or suggestions for us to try? What could cause the CPU to send fewer clock cycles, and why would external unterminated cables affect this?
reason may be excessive i2c bus line capacitive load, max. value is described in
sect.3.9.5 I2C bus characteristics i.MX 8M Mini Applications Processor Datasheet for Consumer Products
and Table 10. Characteristics of the SDA and SCL bus lines I2C specification