Hi, Shai
Thank you for the datasheet.
Based on the provided datasheet RE0 and NRE0 are read-enable pins in differential signaling.
The i.MX NAND interface doesn't have support for a read enable working in differential signaling, but it seems that memory can work for some operations using only NRE0, so I can suggest testing operations using only this pin (as you connect) or changing the memory with a read enable with single-ended support.
About NAND_nREADY is right connected to RNB0 (Ready/Busy), but based on the provided schematic it seems that RNB0 is an input but the datasheet describes the Ready/Busy pin as an output.
In general, the pins are right connected but you have to test as a single-ended read enable pin and review the ready/busy pin as an output.
If you have any questions or concerns, don’t hesitate to let me know.
Best regards,
Brian.