Philip,
For your question: good catch, I have modified the mxc_v4l2_capture.c driver source code, because I think this if statement is incorrect for my case:
/* This may not work on other platforms. Check when adding a new one.*/
pr_debug(" clock_curr=mclk=%d\n", ifparm.u.bt656.clock_curr);
if (ifparm.u.bt656.clock_curr == 0) {
csi_param.clk_mode = IPU_CSI_CLK_MODE_CCIR656_INTERLACED
This construction does not make sense to me, and the comment is vague about it. My sensor (FPGA) provides all signals to the CSI interface, even the PIXCLK. I forced to GATED mode afterwards.
I already found the problem, this seems a second case of bad documentation, very frustrating. The i.MX53 does only seem to care about the HSYNC edge, and expects a full line of contiguous data to arrive on each clock afterwards. This is contrast with the datasheet/RM which says that the HSYNC is ANDed with PIXCLK to derive the (internal) latch signal upon which valid video pixels are clocked in.
This can be verified by making the HSYNC pulse too short. You will notice that the i.MX53 will continue to capture the data after the HSYNC goes low.